SAP5SD-B-G1-R datasheet(54/63 Pages) ETC2

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SAP5S / SAP51

Universal Actuator-Sensor Interface IC

Data Sheet

July 17, 2012

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

54 of 62

In Master/Repeater Mode the SAP5 provides an AS-i power-fail detector. It consists of a comparator directly

connected to the LTGP pin which generates a logic signal in case the voltage at the LTGP pin drops below

VAPF (refer to Table 39). A subsequent digital signal processing of the comparator output signal is performed

as follows:



An anti-bouncing filter removes each signal states shorter than 6

s. This is to eliminate the influence

of AS-i telegrams which are added onto the AS-i DC voltage.



An additional anti-bouncing filter with different filter times for activation and deactivation of the power-

fail signal removes short power-fail pulses.



The AS-i power-fail signal is provided directly active HIGH as signal APF.



Additionally, in Master Mode, the AS-i power-fail signal modulates the RX_DAT signal, whereas the

active state is signaled by logic HIGH level.

Table 39: Master/Repeater Mode Parameter

Symbol

Parameter

Min Max Unit

Note

tloopback

Loopback time in Master Mode

4.9

6.5

s

VAPF

AS-i Power Fail voltage threshold

21.

23.



tAPF_RX_DAT

minimum activation time for signaling of AS-i Power

Fail by use of the RX_DAT signal

640

704

s

tAPF_ON_RX_DAT

release time of the AS-i Power Fail state within the

RX_DAT signal

s

tAPF_APF

minimum activation time for signaling of AS-i Power

Fail by use of the APF signal

704

768

s

tHOLD_APF

AS-i Power Fail hold time

s

tAPF_OFF

delay time after return of the AS-i Power

128

s

tBREAK

break time in case of an erroneous AS-i signal

s

1 Loopback time is the time difference between an edge in the MAN code of signal TX_DAT and the

corresponding edge in the Manchester-code of the signal RX_DAT. The voltage trigger level for measurement

of the edge time is defined by VU5R/2. The actual loopback time may be adjusted by programming the

ID_Code_Extension_2 EEPROM register as described in Table 38.

2 In Master Mode, the AS-i Power Fail state is already signaled by the RX_DAT signal as soon as the power

fail condition is true for a time more than tAPF_RX_DAT. However, in order to start the APF minimum hold state

(tHOLD_APF), the power fail condition must remain true for another time period defined by tAPF_ON_RX_DAT.

Otherwise, the RX_DAT signal returns to its idle state (logic LOW) immediately.

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