SAP5SD-B-G1-R datasheet(46/63 Pages) ETC2

46 / 63 page

SAP5S / SAP51

Universal Actuator-Sensor Interface IC

Data Sheet

July 17, 2012

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

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If at least one of these errors occurs, the received telegram is treated invalid. In this case, the UART will not

generate a Receive Strobe signal. It moves to asynchronous state and wait for a pause at the AS-i line input.

After a pause was detected, the UART is ready to receive the next telegram.

Receive Strobe signals are generally used to validate the correctness of the received data. Receive Strobe

starts the internal processing of a master request. If the UART was in asynchronous state before the signal

was generated, it transforms to synchronous state thereafter. In case the received slave address matches the

stored address of the IC, the transmitter is turned on by the Receive Strobe pulse, letting the output driver

settle smoothly at the operation point (avoiding false pulses at the AS-i line).

4.15. Main State Machine

The Main State Machine controls the overall behavior of the IC. Depending on the configuration data stored in

the E²PROM, the State Machine activates one of the different IC operational modes and controls the digital

I/O ports accordingly. In Slave Mode it processes the received master telegrams and computes the contents

of the slave answer, if required. Table 6 on page 20 lists all master calls that are decoded by the SAP5 in

Slave Mode. To prevent the critical situation in which the IC gets locked in a not allowed state (i.e. by imission

of strong electromagnetic radiation) and thereby could jeopardize the entire system, all prohibited states of the

state machine will lead to an unconditioned logic reset which is comparable to the AS-i call ”Reset Slave

(RES)”.

4.16. Status Registers

Table 32 shows the SAP5 status register content. The use of status bits S0, S1 and S3 is compliant to the AS-

Interface Complete Specification. Status bit S2 is not used. The status register content can be determined by

use of a Read_Status (RDST) master request (refer to Table 6).

Table 32: Status Register Content

Status Register Bit

Sx = 0

Sx = 1

2PROM write accessible

Slave Address stored volatile and/or

2PROM access blocked (write in

progress)

no periphery fault detected,

(input PFAULT = ‘1’),

2PROM Firmware Area and Safety

Area content consistent

periphery fault detected,

(input PFAULT = ‘0’),

parity bit error in E

2PROM Firmware

Area or Safety Area

Static zero

N/A

2PROM content consistent

2PROM contains corrupted data

1 Status Bit S0 is set to ‘1’ as soon as a DELA master request was received and the slave address was

unequal to “0” before. Additionally, it is set for the entire duration of each E

2PROM write access.

4.17. Communication Monitor/Watchdog

The IC contains an independent Communication Monitor that observes the processing of Data_Exchange

(DEXG) and Write_Parameter (WPAR) requests. If no such requests have been processed for more than

94.2ms (+4ms) the Communication Monitor recognizes a No Data/Parameter Exchange status and turns the

red status LED (LED2) on. Any following Data_Exchange or Write_Parameter request will let the

Communication Monitor start over and turn the red status LED off.

The Communication Monitor is only activated at slave addresses unequal to zero (0) and while the IC is

processing the first Write_Parameter request after initialization. It becomes deactivated at any IC Reset or

after the reception of a Delete_Address Request.

Activation of the Communication Watchdog depends on several E²PROM flags and the Parameter Port P0

Output Register

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