SAP5SD-B-G1-R datasheet(36/63 Pages) ETC2

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SAP5S / SAP51

Universal Actuator-Sensor Interface IC

Data Sheet

July 17, 2012

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Table 23: Activation of Synchronous Mode

Synchronous_Data_IO

P2_Sync_Activation

Parameter P2 Ouput Register

Synchronous Mode

OFF

NOTE: The Synchronous Mode is not available if Safety Mode is enabled.

With activated Synchronous Mode, input data sampling as well as output data driving events are moved to

different times synchronized to the polling cycle of the AS-i network. Nevertheless, the communication

principles between master and slave remain unchanged compared to regular operation. Following rules apply:



Data I/O is triggered by the DEXG call to slave with the lowest slave address in the network. Based on

the fact, that a master is calling slaves successively with rising slave addresses, the SAP5 considers

the trigger condition true, if the slave address of a received DEXG call is less than the slave address

of the previous (correctly received) DEXG call.

Data I/O is only triggered, if the slave has (correctly) received data during the last cycle. If the slave

did not receive data (i.e. due to a communication error) the Data Outputs are not changed and no

Data Strobe is generated (arm+fire principle). The inputs however, are always sampled at the trigger

event.



If the slave with the lowest address in the network is operated in the Synchronous Mode, it

postpones the output event for the received data for a full AS-i cycle. This is to keep all output data of

a particular cycle image together.

Note: To make this feature useful, the master shall generate a data output cycle image once before

the start of every AS-i cycle. The image is derived from the input data of the previous cycle(s) and

other control events. Once an AS-i cycle has started, the image shall not change anymore. If A- and

B- slaves are installed in parallel at one address, the master shall address all A-Slaves in one cycle

and all B-Slaves in the other cycle.

The input data, sampled at the slave with the lowest slave address in the network, is sent back to the

master without any delay. Thus, the input data cycle image is fully captured at the end of an AS-i

cycle, just as in networks without any Synchronous Mode slaves. In other words, the input data

sampling point has simply moved to the beginning of the AS-i cycle for all Synchronous Mode slaves.



If the Synchronous Data IO Mode is enabled through EEPROM setting (Synchronous_Data_IO = ‘1’,

P2_Sync_Activation = ‘0’), the first DEXG call that is received by a particular slave after the activation

of the Data Port (Data_Exchange_Disable flag was cleared by a WPAR call) is processed like in

regular operation. This is to capture decent input data for the first slave response and to activate the

outputs as fast as possible.

The Data I/O operation is repeated together with the I/O cycle of the other Synchronous Mode slaves

in the network at the common trigger event. By that, the particular slave has fully reached the

Synchronous Mode.



If the P2_Sync_Activation flag is set to ‘1’ the Synchronous Data IO Mode can be activated or

deactivated during normal operation by sending Write_Parameter calls containing the appropriate

value in P2 (see Table 23).

If the P2 output register changes from ‘1’ to ‘0’ the Synchronous Data IO Mode gets enabled in the

first instance. Real synchronous data I/O operation is reached after reception of the next DEXG call

addressing the slave and the occurrence of the common trigger event. As in standard operation

(Synchronous Data IO Mode is activated by EEPROM setting) the first DEXG still processes a data IO

operation immediately. This is to capture decent input data for the slave response and to activate the

outputs as fast as possible.

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