80960HA datasheet(102/102 Pages) INTEL

102 / 102 page

80960HA/HD/HT

Advance Information Datasheet

Table 26. Data Sheet Version -006 to -007 Revision History

Section

Description

Entire data sheet

Formatted in new template.

“32-Bit Parallel Architecture” on page 1

Revised “1.2 Gbyte Internal Bandwith (75 MHz) to

“1.28 Gbyte ... (80 MHz)”.

Updated legal text.

Section 3.0, “Package Information” on page 6

Added paaragraph two and Table 5.

Table 7 “80960Hx Processor Family Pin Descriptions”

on page 8

Corrected minor typeset and spacing errors.

BREQ; Revised description.

ONCE; last sentence, changed “low” to “high”.

TDI and TMS; removed last sentence, “Pull this pin

low when not in use.”

Figure 2 “80960Hx 168-Pin PGA Pinout — View from

Top (Pins Facing Down)” on page 12

Added insert package marking diagram.

Figure 4 “80960Hx 208-Pin PQ4 Pinout” on page 18

Added insert package marking diagram.

Table 10 “80960Hx PQ4 Pinout — Signal Name

Order” on page 19

Corrected TDO (“O” was zero) and revised

alphabetical ordering.

Table 11 “80960Hx PQ4 Pinout — Pin Number Order”

on page 21

Corrected TDO (“O” was zero) and revised

alphabetical ordering.

Section 4.1, “Absolute Maximum Ratings” on page 29

Revised “VCC” to “VCC5” for “Voltage on Other Pins

...”.

Section 4.5, “VCCPLL Pin Requirements” on page 31

Added section.

Table 21 “80960Hx DC Characteristics” on page 32

Added footnote (1) to “ILO” notes column for “TDO”

pin.

Added footnote (10) to “CIN,COUT and CI/O”pin.

Table 22 “80960Hx AC Characteristics” on page 34

Added overbars where required.

Modified “TDVNH” to list separate specifications for 3.3

V and 5 V.

Modified “TOV2,TOH2 and TTVEL” to reflect specific

80960HA, 80960HD and 80960HT values.

Figure23“ICC Active (Power Supply) vs. Frequency”

on page 43

Changed “5” to “0” on “CLKIN Frequency” axis.

Figure 49 “BREQ and BSTALL Operation” on page 66

Added figure and following text.

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