80960HA datasheet(14/102 Pages) INTEL

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80960HA/HD/HT

Advance Information Datasheet

Table 7.

80960Hx Processor Family Pin Descriptions (Sheet 1 of 4)

Name

Type

Description

A31:2

H(Z)

B(Z)

R(Z)

ADDRESS BUS carries the upper 30 bits of the physical address. A31 is the most

significant address bit and A2 is the least significant. During a bus access, A31:2

identify all external addresses to word (4-byte) boundaries. The byte enable

signals indicate the selected byte in each word. During burst accesses, A3 and A2

increment to indicate successive addresses.

D31:0

I/O

S(L)

H(Z)

B(Z)

R(Z)

DATA BUS carries 32, 16, or 8-bit data quantities depending on bus width

configuration. The least significant bit of the data is carried on D0 and the most

significant on D31. The lower 8 data lines (D7:0) are used when the bus is

configured for 8-bit data. When configured for 16-bit data, D15:0 are used.

DP3:0

I/O

S(L)

H(Z)

B(Z)

R(Z)

DATA PARITY carries parity information for the data bus. Each parity bit is

assigned a group of 8 data bus pins as follows:

DP3 generates/checks parity for D31:24

DP2 generates/checks parity for D23:16

DP1 generates/checks parity for D15:8

DP0 generates/checks parity for D7:0

Parity information is generated for a processor write cycle and is checked for a

processor read cycle. Parity checking and polarity are programmable. Parity

generation/checking is only performed for the size of the data accessed.

PCHK

H(Q)

B(Q)

R(1)

PARITY CHECK indicates the result of a parity check operation. An asserted

PCHK indicates that the previous bus read access resulted in a parity check error.

BE3:0

H(Z)

B(Z)

R(1)

BYTE ENABLES select which of the four bytes addressed by A31:2 are active

during a bus access. Byte enable encoding is dependent on the bus width of the

memory region accessed:

32-bit bus:

BE3 enables D31:24

BE2 enables D23:16

BE1 enables D15:8

BE0 enables D7:0

16-bit bus:

BE3 becomes Byte High Enable (enables D15:8)

BE2 is not used (state is undefined)

BE1 becomes Address Bit 1 (A1)

BE0 becomes Byte Low Enable (enables D7:0)

8-bit bus:

BE3 is not used (state is undefined)

BE2 is not used (state is undefined)

BE1 Address Bit 1 (A1)

BE0 Address Bit 0 (A0)

W/R

H(Z)

B(Z)

R(0)

WRITE/READ is low for read accesses and high for write accesses. W/R

becomes valid during the address phase of a bus cycle and remains valid until the

end of the cycle for non-pipelined accesses. For pipelined accesses, W/R

changes state when the next address is presented.

0= Read

1= Write

D/C

H(Z)

B(Z)

R(0)

DATA/CODE indicates that a bus access is a data access or an instruction

access. D/C has the same timing as W/R.

0 = Code

1= Data

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