80960HA datasheet(15/102 Pages) INTEL

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80960HA/HD/HT

Advance Information Datasheet

SUP

H(Z)

B(Z)

R(1)

SUPERVISOR ACCESS indicates whether the current bus access originates from

a request issued while in supervisor mode or user mode. SUP can beusedby the

memory subsystem to isolate supervisor code and data structures from

non-supervisor access.

0 = Supervisor Mode

1 = User Mode

ADS

H(Z)

B(Z)

R(1)

ADDRESS STROBE indicates a valid address and the start of a new bus access.

ADS is asserted for the first clock of a bus access.

READY

S(L)

READY, when enabled for a memory region, is asserted by the memory

subsystem to indicate the completion of a data transfer. READY is used to

indicate that read data on the bus is valid, or that a write transfer has completed.

READY works in conjunction with the internal wait state generator to

accommodate various memory speeds. READY is sampled after any programmed

wait states:

During each data cycle of a burst access

During the data cycle of a non-burst access

BTERM

S(L)

BURST TERMINATE, when enabled for a memory region, is asserted by the

memory subsystem to terminate a burst access in progress. When BTERM is

asserted, the current burst access is terminated and another address cycle

occurs.

WAIT

H(Z)

B(Z)

R(1)

WAIT indicates the status of the internal wait-state generator. WAIT is asserted

when the internal wait state generator generates NWAD,NRAD,NWDD and NRDD

wait states. WAIT canbeusedtoderivea writedatastrobe.

BLAST

H(Z)

B(Z)

R(1)

BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the

last data transfer of burst and non-burst accesses after the internal wait-state

generator reaches zero. BLAST remains active as long as wait states are inserted

via the READY pin. BLAST becomes inactive after the final data transfer in a bus

cycle.

DT/R

H(Z)

B(Z)

R(0)

DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is

used with DEN to provide control for data transceivers connected to the data bus.

DT/R is driven low to indicate the processor expects data (a read cycle). DT/R is

driven high when the processor is “transmitting” data (a store cycle). DT/R only

changes state when DEN is high.

0 = Data Receive

1 = Data Transmit

DEN

H(Z)

B(Z)

R(1)

DATA ENABLE indicates data transfer cycles during a bus access. DEN is

asserted at the start of the first data cycle in a bus access and de-asserted at the

end of the last data cycle. DEN remains asserted for an entire bus request, even

when that request spans several bus accesses. For example, a ldq instruction

starting at an unaligned quad word boundary is one bus request spanning at least

two bus accesses. DEN remains asserted throughout all the accesses (including

ADS states) and de-asserts when the Iqd instruction request is satisfied. DEN is

used with DT/R to provide control for data transceivers connected to the data bus.

DEN remains asserted for sequential reads from pipelined memory regions.

LOCK

H(Z)

B(Z)

R(1)

BUS LOCK indicates that an atomic read-modify-write operation is in progress.

LOCK may be used by the memory subsystem to prevent external agents from

accessing memory that is currently involved in an atomic operation (e.g., a

semaphore). LOCK is asserted in the first clock of an atomic operation and

de-asserted when BLAST is deasserted in the last bus cycle.

Table 7.

80960Hx Processor Family Pin Descriptions (Sheet 2 of 4)

Name

Type

Description

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