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80960HA 数据表(PDF) 65 Page - Intel Corporation |
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80960HA 数据表(HTML) 65 Page - Intel Corporation |
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65 / 102 page ![]() 80960HA/HD/HT Advance Information Datasheet 59 Figure 42. Non-Burst, Pipelined Read Request with Wait States, 32-Bit Bus ADS A31:4, SUP, CT3:0, D/C, W/R BLAST DT/R DEN A3:2 WAIT D31:0, CLKIN BE3:0 A1 A' D 1 D ' IN D' Valid Valid Invalid IN D LOCK Valid Valid Invalid DP3:0 1. Non-pipelined request concludes, pipelined reads begin 2. Pipelined reads conclude, non-pipelined requests begin PCHK 2 1 Burst Bus Width Odd Parity NXDA NWDD NWAD NRDD 29 28 21 24 23-22 20 12-8 19-16 15-14 7-6 4-0 Disabled 0 ON 1 X xxxx 32-Bit X x Enabled 1 X xx X xxxxx X xx X x 1 00001 Function Bit Value External Ready Control Pipe- Lining Parity Enable NRAD NOTE: Bits 31-30, 27-25, 13, and 5 are reserved. 10 Invalid PMCON |
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