80960HA datasheet(42/102 Pages) INTEL

42 / 102 page

80960HA/HD/HT

Advance Information Datasheet

Table 23. AC Characteristics Notes

NOTES:

1. See Section 4.8, “AC Timing Waveforms” on page 38 for waveforms and definitions.

2. See Figure 25 “Output Delay or Hold vs. Load Capacitance” on page 44 for capacitive derating information

for output delays and hold times.

3. See Figure 22 “Rise and Fall Time Derating at 85°C and Minimum VCC” on page 43 for capacitive derating

information for rise and fall times.

4. Where N is the number of NRAD,NRDD,NWAD or NWDD wait states that are programmed in the Bus

Controller Region Table. WAIT never goes active when there are no wait states in an access.

5. N = Number of wait states inserted with READY.

6. These specifications are guaranteed by the processor.

7. These specifications must be met by the system for proper operation of the processor.

8. RESET is an asynchronous input that has no required setup and hold time for proper operation. However,

to guarantee the device exits the reset mode synchronized to a particular clock edge, the rising edge of

RESET must meet setup and hold times to the rising edge of the CLKIN.

9. The interrupt pins are synchronized internally by the 80960Hx. They have no required setup or hold times

for proper operation. These pins are sampled by the interrupt controller every clock and must be active for

at least two consecutive CLKIN rising edges when asserting them asynchronously. To guarantee

recognition at a particular clock edge, the setup and hold times shown must be met.

10.Relative Output timings are not tested.

11.Not tested.

12.The processor minimizes changes to the bus signals when transitioning from a bus cycle to an idle bus for

the following signals: A31:4, SUP,CT3:0,D/C,LOCK,W/R, BE3:0.

Table 24. 80960Hx Boundary Scan Test Signal Timings

Symbol

Parameter

Min

Max

Units

Notes

TBSF

TCK Frequency

MHz

TBSC

TCK Period

125

Infinite

TBSCH

TCK High Time

Measured at 1.5 V (1)

TBSCL

TCK Low Time

Measured at 1.5 V (1)

TBSCR

TCK Rise Time

0.8 V to 2.0 V (1)

TBSCF

TCK Fall Time

2.0 V to 0.8 V (1)

TBSIS1

Input Setup to TCK —

TDI, TMS

8ns

TBSIH1

Input Hold from TCK —

TDI, TMS

TBSOV1

TDO Valid Delay

TBSOF1

TDO Float Delay

(1)

TBSOV2

All Outputs (Non-Test)

Valid Delay

330

Relative to TCK

TBSOF2

All Outputs (Non-Test)

Float Delay

Relative to TCK (1)

TBSIS2

Input Setup to TCK - All

Inputs (Non-Test)

8ns

TBSIH2

Input Hold from TCK - All

Inputs (Non-Test)

NOTE:

1. Not tested.

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