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UPD703003 数据表(PDF) 29 Page - NEC |
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UPD703003 数据表(HTML) 29 Page - NEC |
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29 / 82 page  29 µPD703003 Data Sheet U12261EJ2V1DS00 10. PWM UNIT The features of the PWM unit are shown below. • PWMn: 2 channels • Selectable active level for PWMn output pulse • Operating clock selectable as φ, φ/2, φ/4, φ/8, or φ/16 (φ : internal system clock) • PWMn output resolution selectable as 8, 9, 10, or 12 bits Remark n = 0, 1 The configuration of the PWM unit is shown below. Figure 10-1. Block Diagram of PWM Unit Note Priority to reset Remark n = 0, 1 φ : internal system clock TMPn (12 bits) Comparator CMPn (12 bits) PWMn (12 bits) /2 /4 /8 /16 Overflow Match 7 8 9 11 0-7 0-8 0-9 0-11 SQ RNote ALVn PWMn φ φ φ φ φ |
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