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UPD703003 数据表(PDF) 49 Page - NEC |
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UPD703003 数据表(HTML) 49 Page - NEC |
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49 / 82 page  49 µPD703003 Data Sheet U12261EJ2V1DS00 Instruction Set List Instruction Mnemonic Operand Opcode Operation Flags group CY OV SZ SAT Load/store SLD.B disp7[ep], reg2 r r r r r 0 110 ddd ddd d adr ← ep + zero-extend (disp7) instructions GR[reg2] ← sign-extend (Load-memory (adr, Byte)) SLD.H disp8[ep], reg2 r r r r r 1 000 ddd ddd d adr ← ep + zero-extend (disp8) Note 1 GR[reg2] ← sign-extend (Load-memory (adr, Halfword)) SLD.W disp8[ep], reg2 r r r r r 1 010 ddd ddd 0 adr ← ep + zero-extend (disp8) Note 2 GR[reg2] ← Load-memory (adr, Word) LD.B disp16[reg1], reg2 r r r r r 1 110 00 RRRRR adr ← GR[reg1] + sign-extend (disp16) ddd ddd ddd ddd ddd d GR[reg2] ← sign-extend (Load-memory (adr, Byte)) LD.H disp16[reg1], reg2 r r r r r 1 110 01 RRRRR adr ← GR[reg1] + sign-extend (disp16) d d d d d d d d d d d d d d d 0 GR[reg2] ← sign-extend (Load-memory (adr, Halfword)) Note 3 LD.W disp16[reg1], reg2 r r r r r 1 110 01 RRRRR adr ← GR[reg1] + sign-extend (disp16) ddd ddd ddd ddd ddd 1 GR[reg2] ← Load-memory (adr, Word) Note 3 SST.B reg2, disp7[ep] r r r r r 0 111 ddd ddd d adr ← ep + zero-extend (disp7) Store-memory (adr, GR[reg2], Byte) SST.H reg2, disp8[ep] r r r r r 1 001 ddd ddd d adr ← ep + zero-extend (disp8) Note 1 Store-memory (adr, GR[reg2], Halfword) SST.W reg2, disp8[ep] r r r r r 1 010 ddd ddd 1 adr ← ep + zero-extend (disp8) Note 2 Store-memory (adr, GR[reg2], Word) ST.B reg2, disp16[reg1] r r r r r 1 110 10 RRRRR adr ← GR[reg1] + sign-extend (disp16) ddd ddd ddd ddd ddd d Store-memory (adr, GR[reg2], Byte) ST.H reg2, disp16[reg1] r r r r r 1 110 11 RRRRR adr ← GR[reg1] + sign-extend (disp16) ddd ddd ddd ddd ddd 0 Store-memory (adr, GR[reg2], Halfword) Note 3 ST.W reg2, disp16[reg1] r r r r r 1 110 11 RRRRR adr ← GR[reg1] + sign-extend (disp16) ddd ddd ddd ddd ddd 1 Store-memory (adr, GR[reg2], Word) Note 3 Arithmetic MOV reg1, reg2 r r r r r 0 000 00 RRRRR GR[reg2] ← GR[reg1] operation MOV imm5, reg2 r r r r r 0 100 00 i i i i i GR[reg2] ← sign-extend (imm5) instructions MOVHI imm16, reg1, reg2 r r r r r 1 100 10 RRRRR GR[reg2] ← GR[reg1] + (imm16 || 016) iii iii iii iii iii i MOVEA imm16, reg1, reg2 r r r r r 1 100 01 RRRRR GR[reg2] ← GR[reg1] + sign-extend (imm16) iii iii iii iii iii i ADD reg1, reg2 r r r r r 0 011 10 RRRRR GR[reg2] ← GR[reg2] + GR[reg1] ×× × × ADD imm5, reg2 r r r r r 0 100 10 i i i i i GR[reg2] ← GR[reg2] + sign-extend (imm5) ×× × × ADDI imm16, reg1, reg2 r r r r r 1 100 00 RRRRR GR[reg2] ← GR[reg1] + sign-extend (imm16) ×× × × iii iii iii iii iii i SUB reg1, reg2 r r r r r 0 011 01 RRRRR GR[reg2] ← GR[reg2] – GR[reg1] ×× × × SUBR reg1, reg2 r r r r r 0 011 00 RRRRR GR[reg2] ← GR[reg1] – GR[reg2] ×× × × Notes 1. ddddddd = high-order 7 bits of disp8 2. dddddd = high-order 6 bits of disp8 3. ddddddddddddddd = high-order 15 bits of disp16 |
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