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UPD703003 数据表(PDF) 72 Page - NEC |
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UPD703003 数据表(HTML) 72 Page - NEC |
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72 / 82 page ![]() µPD703003 72 Data Sheet U12261EJ2V1DS00 (9) CSI timing (1/2) (a) Master mode (i) Timing of CSI0 to CSI2 Parameter Symbol Conditions 25-MHz Version 33-MHz Version Units MIN. MAX. MIN. MAX. SCKn cycle <67> tCYSK1 Output 160 120 ns SCKn high-level width <68> tWSKH1 Output 0.5tCYSK1 – 20 0.5tCYSK1 – 20 ns SCKn low-level width <69> tWSKL1 Output 0.5tCYSK1 – 20 0.5tCYSK1 – 20 ns SIn setup time (to SCKn ↑) <70> tSSISK1 50 50 ns SIn hold time (from SCKn ↑) <71> tHSKSI1 00 ns SOn output delay time (to SCKn ↓) <72> tDSKSO1 18 18 ns SOn output hold time (from SCKn ↑) <73> tHSKSO1 0.5tCYSK1 – 5 0.5tCYSK1 – 5 ns Remark n = 0 to 2 (ii) Timing of CSI3 Parameter Symbol Conditions 25-MHz Version 33-MHz Version Units MIN. MAX. MIN. MAX. SCK3 cycle <67> tCYSK3 Output RL = 1.5 k Ω 500 500 ns SCK3 high-level width <68> tWSKH3 Output CL = 50 pF 0.5tCYSK3 – 150 0.5tCYSK3 – 150 ns SCK3 low-level width <69> tWSKL3 Output 0.5tCYSK3 – 70 0.5tCYSK3 – 70 ns SI3 setup time (to SCK3 ↑) <70> tSSISK3 100 100 ns SI3 hold time (from SCK3 ↑) <71> tHSKSI3 50 50 ns SO3 output delay time (to SCK3 ↓) <72> tDSKSO3 RL = 1.5 k Ω 150 150 ns SO3 output hold time (from SCK3 ↑) <73> tHSKSO3 CL = 50 pF tWSKH3 tWSKH3 ns Remark RL and CL are the load resistance and load capacitance of the output line for SCK3 and SO3. (b) Slave mode (i) Timing of CSI0 to CSI2 Parameter Symbol Conditions 25-MHz Version 33-MHz Version Units MIN. MAX. MIN. MAX. SCKn cycle <67> tCYSK2 Input 160 120 ns SCKn high-level width <68> tWSKH2 Input 50 30 ns SCKn low-level width <69> tWSKL2 Input 50 30 ns SIn setup time (to SCKn ↑) <70> tSSISK2 10 10 ns SIn hold time (from SCKn ↑) <71> tHSKSI2 10 10 ns SOn output delay time (to SCKn ↓) <72> tDSKSO2 45 45 ns SOn output hold time (from SCKn ↑) <73> tHSKSO2 tWSKH2 tWSKH2 ns Remark n = 0 to 2 |
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