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UPD703003 数据表(PDF) 73 Page - NEC |
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UPD703003 数据表(HTML) 73 Page - NEC |
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73 / 82 page ![]() 73 µPD703003 Data Sheet U12261EJ2V1DS00 (9) CSI timing (2/2) (ii) Timing of CSI3 Parameter Symbol Conditions 25-MHz Version 33-MHz Version Units MIN. MAX. MIN. MAX. SCK3 cycle <67> tCYSK4 Input 500 500 ns SCK3 high-level width <68> tWSKH4 Input 100 100 ns SCK3 low-level width <69> tWSKL4 Input 180 180 ns SI3 setup time (to SCK3 ↑) <70> tSSISK4 100 100 ns SI3 hold time (from SCK3 ↑) <71> tHSKSI4 50 50 ns SO3 output delay time (to SCK3 ↓) <72> tDSKSO4 RL = 1.5 k Ω 150 150 ns SO3 output hold time (from SCK3 ↑) <73> tHSKSO4 CL = 50 pF tWSKH4 tWSKH4 ns Remark RL is the load resistance and CL is the load capacitance of the output line for SCK3 and SO3. SCKn (I/O) SIn (Input) SOn (output) <67> <69> <68> <70> <71> <72> <73> Input data Output data Remarks 1. Broken line indicates high impedance. 2. n = 0 to 3 |
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