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UPD703003 数据表(PDF) 64 Page - NEC |
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UPD703003 数据表(HTML) 64 Page - NEC |
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64 / 82 page  µPD703003 64 Data Sheet U12261EJ2V1DS00 (5) Read timing (1/2) Parameter Symbol Conditions 25-MHz Version 33-MHz Version Units MIN. MAX. MIN. MAX. CLKOUT ↑ → address delay time <20> tDKA 3 20 3 20 ns CLKOUT ↑ → R/W, UBEN, LBEN delay time <78> tDKA2 –2 +13 –2 +13 ns CLKOUT ↑ → address float delay time <21> tFKA 3 15 3 15 ns CLKOUT ↓ → ASTB delay time <22> tDKST –2 +13 –2 +13 ns CLKOUT ↑ → DSTB delay time <23> tDKD –2 +13 –2 +13 ns Data input setup time (to CLKOUT ↑) <24> tSIDK 77 ns Data input hold time (from CLKOUT ↑) <25> tHKID 55 ns WAIT setup time (to CLKOUT ↓) <26> tSWTK 88 ns WAIT hold time (from CLKOUT ↓) <27> tHKWT 55 ns Address hold time (from CLKOUT ↑) <28> tHKA 00 ns Address setup time (to ASTB ↓) <29> tSAST 0.5T – 10 0.5T – 10 ns Address hold time (from ASTB ↓) <30> tHSTA 0.5T – 10 0.5T – 10 ns DSTB ↓ → address float delay time <31> tFDA 00 ns Data input setup time (to address) <32> tSAID (2 + n)T – 20 (2 + n)T – 20 ns Data input setup time (to DSTB ↓) <33> tSDID (1 + n)T – 20 (1 + n)T – 20 ns ASTB ↓ → DSTB↓ delay time <34> tDSTD 0.5T – 10 0.5T – 10 ns Data input hold time (from DSTB ↑) <35> tHDID 00 ns DSTB ↑ → address output delay time <36> tDDA (1 + i)T – 3 (1 + i)T – 3 ns DSTB ↑ → ASTB↑ delay time <37> tDDSTH 0.5T – 10 0.5T – 10 ns DSTB ↑ → ASTB↓ delay time <38> tDDSTL (1.5 + i)T – 10 (1.5 + i)T – 10 ns DSTB low-level width <39> tWDL (1 + n)T – 10 (1 + n)T – 10 ns ASTB high-level width <40> tWSTH T – 10 T – 10 ns WAIT setup time (to address) <41> tSAWT1 n ≥ 1 1.5T – 20 1.5T – 20 ns <42> tSAWT2 (1.5 + n)T – 20 (1.5 + n)T – 20 ns WAIT hold time (from address) <43> tHAWT1 n ≥ 1 (0.5 + n)T (0.5 + n)T ns <44> tHAWT2 (1.5 + n)T (1.5 + n)T ns WAIT setup time (to ASTB ↓) <45> tSSTWT1 n ≥ 1 T – 15 T – 15 ns <46> tSSTWT2 (1 + n)T – 15 (1 + n)T – 15 ns WAIT hold time (from ASTB ↓) <47> tHSTWT1 n ≥ 1nT nT ns <48> tHSTWT2 (1 + n)T (1 + n)T ns Remarks 1. T = tCYK 2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may vary when using the programmable wait insertion function. 3. i indicates the number of idle states (0 or 1) that are inserted after a read cycle. 4. Maintain at least one of the two data input hold times, either tHKID (<25>) or tHDID (<35>). |
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