UPD703003 datasheet(3/82 Pages) NEC

3 / 82 page

µPD703003

Data Sheet U12261EJ2V1DS00

PIN NAMES

A16 to A19

: Address Bus

P30 to P37

: Port3

AD0 to AD15

: Address/Data Bus

P40 to P47

: Port4

ADTRG

: AD Trigger Input

P50 to P57

: Port5

ANI0 to ANI7

: Analog Input

P60 to P63

: Port6

ANO0, ANO1

: Analog Output

P70 to P77

: Port7

ASTB

: Address Strobe

P90 to P96

: Port9

AVDD

: Analog VDD

P110 to P117

: Port11

AVREF1 to AVREF3

: Analog Reference Voltage

PWM0, PWM1

: Pulse Width Modulation

AVSS

: Analog VSS

RESET

: Reset

CVDD

: Power Supply for Clock Generator

R/W

: Read/Write Status

CVSS

: Ground for Clock Generator

RXD0, RXD1

: Receive Data

CKSEL

: Clock Select

SCK0 to SCK3

: Serial Clock

CLKOUT

: Clock Output

SI0 to SI3

: Serial Input

DSTB

: Data Strobe

SO0 to SO3

: Serial Output

HLDAK

: Hold Acknowledge

TO110, TO111,

: Timer Output

HLDRQ

: Hold Request

TO120, TO121,

: Internally Connected

TO130, TO131,

INTP110 to INTP113, : Interrupt Request from Peripherals

TO140, TO141

INTP120 to INTP123,

TCLR11 to TCLR14 : Timer Clear

INTP130 to INTP133,

TI11 to TI14

: Timer Input

INTP140 to INTP143

TXD0, TXD1

: Transmit Data

LBEN

: Lower Byte Enable

UBEN

: Upper Byte Enable

MODE

: Mode

WAIT

: Wait

NMI

: Non-maskable Interrupt Request

X1, X2

: Crystal

P00 to P07

: Port0

VDD

: Power Supply

P10 to P17

: Port1

VSS

: Ground

P20 to P27

: Port2

UPD703003 数据表(PDF) 3 Page - NEC

UPD703003 数据表(HTML) 3 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

数据表下载