PM0215 datasheet(64/91 Pages) STMICROELECTRONICS

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The STM32 Cortex-M0 instruction set

PM0215

64/91

Doc ID 022979 Rev 1

3.7.5

ISB

Instruction synchronization barrier.

Syntax

ISB

Operation

ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so

that all instructions following the ISB are fetched from cache or memory again, after the ISB

instruction has been completed.

Restrictions

None

Condition flags

This instruction does not change the flags.

Examples

ISB

; Instruction Synchronisation Barrier

3.7.6

MRS

Move the contents of a special register to a general-purpose register.

Syntax

MRS Rd, spec_reg

where:

●

‘Rd’ is the general-purpose destination register.

●

‘spec_reg’ is one of the special-purpose registers: APSR, IPSR, EPSR, IEPSR,

IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, or CONTROL.

Operation

MRS stores the contents of a special-purpose register to a general-purpose register. MRS

can be combined with the MSR instruction to produce read-modify-write sequences, which

are suitable for modifying a specific flag in the PSR. See MSR on page 65.

Restrictions

Rd must not be SP or PC.

Condition flags

This instruction does not change the flags.

Examples

MRS

R0, PRIMASK

; Read PRIMASK value and write it to R0

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