PM0215 datasheet(20/91 Pages) STMICROELECTRONICS

20 / 91 page

The STM32 Cortex-M0 processor

PM0215

20/91

Doc ID 022979 Rev 1

2.2.3

Behavior of memory accesses

The behavior of accesses to each region in the memory map is:

The Code, SRAM, and external RAM regions can hold programs.

2.2.4

Software ordering of memory accesses

The order of instructions in the program flow does not always guarantee the order of the

corresponding memory transactions. This is because:

●

The processor can reorder some memory accesses to improve efficiency, providing this

does not affect the behavior of the instruction sequence.

●

Memory or devices in the memory map have different wait states

●

Some memory accesses are buffered or speculative.

Section 2.2.2: Memory system ordering of memory accesses on page 19 describes the

cases where the memory system guarantees the order of memory accesses. Otherwise, if

the order of memory accesses is critical, software must include memory barrier instructions

to force that ordering. The processor provides the following memory barrier instructions:

Table 11.

Memory access behavior

Address

range

Memory

region

Memory

type(1)

See Memory regions, types and attributes on page 19 for more information.

XN(1)

Description

0x00000000-

0x1FFFFFFF

Code

Normal

Executable region for program code. Can also put

data here.

0x20000000-

0x3FFFFFFF

SRAM

Normal

Executable region for data. Can also put code

here.

0x40000000-

0x5FFFFFFF

Peripheral

Device

External device memory

0x60000000-

0x9FFFFFFF

External

RAM

Normal

Executable region for data.

0xA0000000-

0xDFFFFFFF

External

device

Device

External device memory

0xED000000-

0xED0FFFFF

Private

Peripheral

Bus

Strongly-

ordered

This region includes the NVIC, System timer, and

system control block. Only word accesses can be

used in this region.

0xED100000-

0xFFFFFFFF

Device

This region includes all the STM32 standard

peripherals.

DMB

The Data Memory Barrier instruction ensures that outstanding memory transactions

complete before subsequent memory transactions. See DMB on page 63.

DSB

The Data Synchronization Barrier instruction ensures that outstanding memory

transactions complete before subsequent instructions execute. See DSB on

page 63.

ISB

The Instruction Synchronization Barrier ensures that the effect of all completed

memory transactions is recognizable by subsequent instructions. See ISB on

page 64.

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