CMX608 datasheet(34/70 Pages) CMLMICRO

34 / 70 page

RALCWI Vocoder

CMX608/CMX618/CMX638

 2014 CML Microsystems Plc

D/608_18_38/11

AOG register address $06 (CMX618/CMX638 only. No function on CMX608.)

OUTPUT GAIN SWITCH

OUTPUT GAIN

This is the analogue output gain control register. The output level should be chosen to avoid

unnecessary distortion in the output amplifier. This gain block follows the DAC, which is a sigma-

delta design with a sampling frequency of 2.4MHz and an on-chip reconstruction filter. An external

RC filter could be added across the OUTP and OUTN pins, if clock noise needs further reduction.

Bits 0 to 3

These bits control the output gain stage according to the following table:

OUTPUT

GAIN

Bit 3

Bit 2

Bit 1

Bit 0

Gain (dB)

-14 (default)

-12

-10

-8

-6

-4

-2

Bits 4 to 6

These bits are unused and should be cleared to '0'.

Bit 7

A '0' in this bit sets the earpiece gain to 0dB. A '1' in this bit sets the earpiece gain

OUTPUT

to +6dB. A further 6dB of gain can be achieved by using both audio outputs. As

GAIN

these outputs are in anti-phase, connecting the earpiece across them will provide

SWITCH

6dB more gain, as well as saving a dc blocking capacitor. See Figure 7.

CMX608 数据表(PDF) 34 Page - CML Microcircuits

CMX608 数据表(HTML) 34 Page - CML Microcircuits

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