CMX608 datasheet(53/70 Pages) CMLMICRO

53 / 70 page

RALCWI Vocoder

CMX608/CMX618/CMX638

 2014 CML Microsystems Plc

D/608_18_38/11

STATUS register address $40

RDY

SVC

VDW

PLV

DFDA

EFDA

VDA

This read-only register indicates that the device has data or needs servicing. The device can be

used in an interrupt driven mode or a polled mode.

If being used in an interrupt driven mode, after a C-BUS interrupt, this register should be read to

establish the reason for the interrupt. An interrupt will only be generated if the corresponding bit of

the IRQENAB register ($1F) is also set to '1'. If the device is being used in a polled mode, then

this register should be read at regular intervals. The register is cleared to '0' after it is read. It is

possible for more than one bit to be set to '1', so each bit should be dealt with as appropriate. Bits

marked 'X' may get set during normal operation. These should be read and ignored.

Bit 0

Vocoder data available. When this bit is set to '1' a packet of encoded voice is

VDA

ready to be read from the ENCFRAME register ($30).

Bit 1

Encoder Frame Data available. When this bit is set to '1', the encoder has

EFDA

finished encoding a 20ms frame and has updated the EFRAMEDATA register

($38), so the host can determine if the frame contained voice, DTMF or a single

tone and obtain any associated data.

Bit 2

Decoder Frame Data available. When this bit is set to '1', the decoder has

DFDA

finished decoding a 20ms frame and has updated the DFRAMEDATA register

($37), so the host can determine if the frame contained voice, DTMF or a single

tone and obtain any associated data.

Bits 3 to 5

These bits have an un-defined state.

Bit 6

Peak Level sample for the last 20ms frame available. When this bit is set to '1', the

PLV

peak sample value for the last 20ms frame of encoded audio has been updated.

This value may be read from the PLEVEL ($31) register.

Bit 7

This bit has an un-defined state.

Bit 8

Vocoder Data Wanted. When this bit is set to '1' the device is ready to accept

VDW

another packet of data for decoding. Prior to entering decode mode, the high and

low watermarks should be programmed into VDWHLWM register ($1E) and the

Vocoder Data Wanted bit (DVDW) should be set to '1' in the VCTRL register

($11).

Bits 9 to 13

These bits have an un-defined state.

Bit 14

Service. When this bit is set to '1' it indicates that the device has completed a

SVC

service request and that the status of the request can be read from the SVCACK

($2E) register. This bit is also used to indicate that a write to the DTMFATTEN

($0A) register has completed. In this latter case, the SVCACK register need not be

read.

Bit 15

Ready. When this bit is set to '1' it indicates that the device is ready to accept

RDY

commands after certain time consuming operations. This bit will be set to '1' after

the following operations:

CMX608 数据表(PDF) 53 Page - CML Microcircuits

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