CMX608 datasheet(19/70 Pages) CMLMICRO

19 / 70 page

RALCWI Vocoder

CMX608/CMX618/CMX638

 2014 CML Microsystems Plc

D/608_18_38/11

Figure 12 Single Frame Packet Decoding with Host Jitter (Increased IDD)

Figure 12 is the same as the previous figure, but with an increased initial decoder delay. As can be seen,

the CODEC is no longer starved of samples.

5.3.2.

Multiple Frame Packet with FEC, but without STD or DTMF

This is the most suitable configuration for use in a wireless system, where the channel is prone to bit

errors. Two modes are available:

3 frame packet, which represents 60ms of voice. This mode is most suitable for TDMA/DMR.

4 frame packet, which represents 80ms of voice. This mode is most suitable for FDMA/DMR.

For each of these modes, the packets may contain either hard-bits or soft-bits.

Figure 13 shows a timed delivery method for the 3 frame mode, although the principal applies equally to

the 4 frame mode. As in the above examples, if the host has some algorithmic jitter (which affects the

exact time of packet delivery), then the IDD register should be used to increase the initial decoder delay.

Figure 13 Multiple Frame Packet Decoding

CMX608 数据表(PDF) 19 Page - CML Microcircuits