CMX608 datasheet(46/70 Pages) CMLMICRO

46 / 70 page

RALCWI Vocoder

CMX608/CMX618/CMX638

 2014 CML Microsystems Plc

D/608_18_38/11

5.10.4.

16-bit Write-Only Registers

VCTRL register address $11 (also MVCTRL register address $3C)

This write-only register controls the Vocoder when it is operating. A change in the state of these

bits may take up to 20ms before any effect is observed. The VCTRL register is mirrored by the

MVCTRL register ($3C). This read-only register holds the last value written to the VCTRL ($11)

used as confirmation that a write command to a 16-bit C-BUS register is working.

After the VCTRL command has completed, bit 15 of the STATUS register ($40) will be set to '1'

and, if enabled, IRQN will go low. No other C-BUS registers should be read or written whilst this

command is in progress.

Bit 0

Decoder Enable: If this bit is set to '1' the device will accept frames of vocoded

DEC

audio, decode them, and send the samples to the D/A converter. If this bit is

cleared to '0', any supplied frames will be ignored.

Bit 1

Encoder Enable: If this bit is set to '1' the device will collect samples from the A/D

ENC

converter, encode them and send the vocoded frames to the streaming

ENCFRAME register ($30). If this bit is cleared to '0', no vocoded frames of audio

will be produced.

Note: Setting both DEC and ENC to '1' is the same as setting them both to' '0, as full duplex

operation is not possible with the CMX608/CMX618. In the CMX638, DEC and ENC bits can be

set as above, for half-duplex operation, or both DEC and ENC should be set to '1' for full-duplex

operation. When operating in full-duplex, neither DTMF nor STD functions are supported.

Bit 2

Repeater Function Enable: If this bit is set to '1' the device will re-apply FEC to the

FECLOOP

previously supplied FEC encoded frame, after error correction, and then send it to

the streaming ENCFRAME register ($30). This allows the device to be used in a

repeater. If this bit is cleared to '0', this function is turned off.

This bit is ignored if the ENC bit is set to '1'. If the DEC bit is set to '1', the

supplied frames will also be decoded and sent to the D/A converter.

Bit 3

Packet Loss Concealment (PLC): If this bit is set to '1' the

device’s decoder will

PLC

attempt to conceal badly corrupted frames by using a special PLC procedure. If

this bit is cleared to '0', PLC will not be done.

Bit 4

Vocoder Data Wanted: If this bit is set to '1', the device will indicate that it is able

DVDW

to accept another Vocoder frame for decoding, by setting the VDW bit (bit 8) in

the STATUS register ($40). If this bit is cleared to '0', this function is disabled.

ESTDP

ESTDD

EDTMFD

DSTDP

DSTDG

DSTDD

DDTMFG

DDTMFD

DVDW

PLC

FECLOOP

ENC

DEC

CMX608 数据表(PDF) 46 Page - CML Microcircuits

CMX608 数据表(HTML) 46 Page - CML Microcircuits

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