CMX608 datasheet(14/70 Pages) CMLMICRO

14 / 70 page

RALCWI Vocoder

CMX608/CMX618/CMX638

 2014 CML Microsystems Plc

D/608_18_38/11

The CMX608 (and the CMX618/CMX638, if the internal CODEC is not selected) provides a synchronous

serial port (SSP), enabling a wide range of external CODECs to be used with this device. Two digital

outputs, EEC and REC, can be used to enable and reset the external CODEC. They are controlled by bit 0

(EEC) and bit 1 (REC) of the EXCODECCONT register ($0B). On the CMX618/CMX638 only, when the

internal CODEC is selected, these pins are available as uncommitted digital outputs instead.

In CMX608/CMX618/CMX638, DTMF and single tones (STD) can be sent and received reliably over a

noisy channel by using the special control codes, see section 5.7.

Both devices feature a DTX

(Discontinuous Transmission) mode, where an integral Voice Activity Detector in the encoder will send SID

(Silence Insertion Description) data to the decoder, which will perform Comfort Noise Generation.

The CMX608 and CMX618 devices can operate in a mode that reduces the current consumption when the

device is not actively being used, at the expense of a small reduction in maximum C-BUS SCLK frequency

and an increase in the difference between the peaks and troughs of current consumption when running.

This mode is known as 'clock-throttling', where the vocoder's internal clock rate is automatically set to a

quarter of its normal value when the device is waiting for samples or packets, i.e. not actively engaged in

encoding or decoding. Clock throttling is not available on the CMX638.

This mode is enabled by setting bit 4 of the POWERSAVE register ($09) to '1' after the device has been

reset. The typical overall current consumption with "clock throttling" enabled can be calculated from the

following figures:

(3.3V) IDD Total = IDD IODigital + IDD Analogue + IDD Analogue PA = 7.8 mA when encoding

(3.3V) IDD Total = IDD IODigital + IDD Analogue + IDD Analogue PA = 4.1 mA when decoding.

(1.8V) IDD Total = IDD Digital = 33.0 mA when encoding and = 20.0 mA when decoding

For the CMX638, clock throttling is not possible, so the typical Full-duplex current consumption figures are:

(3.3V) IDD Total = IDD IODigital + IDD Analogue + IDD Analogue PA = 11.3 mA

(1.8V) IDD Total = IDD Digital = 49.0 mA

5.1.

Initialisation

On first applying power, three actions have to be performed: the crystal oscillator has to start up (if used),

the bias chain has to be powered up (CMX618/CMX638 only), so that the decoupling capacitor (C14) has

charged to AVDD / 2, and on-chip digital circuits have to be reset into a known state. The crystal oscillator

typically takes much less than 20ms to start up, but the actual time will depend on the ESR of the crystal

used. With the components shown in Figure 3, the BIAS pin will take 100ms typically to reach its steady-

state value of AVDD / 2. There are two sources of reset:

pulling the RESETN signal (pin 30) to '0' for at least 200ns, then returning it to '1' (the pin does not

have an internal pullup resistor). Note that the device does not have an automatic power-up reset.

writing to the C-BUS RESET register ($01). This is a 1-byte command which has no data.

A hard reset (taking RESETN low) will also force the ENABXTAL signal low, which disables the clock and

powersaves the crystal oscillator. On first applying power, the RESETN pin should be held low until all the

power supplies have stabilised, to ensure correct operation of the device. When coming out of a hard

reset, the device needs the crystal oscillator to be working, then counts 65,536 clock cycles (= 5.4ms delay

with a 12.0MHz clock), then automatically performs a soft reset by writing to the C-BUS RESET register.

A soft reset (writing to the RESET register) will clear all registers to '0', unless noted otherwise

– in which

case the default settings are restored. The device will be ready to accept C-BUS commands approximately

1.5ms after completion of the soft reset action and will indicate that it is ready by setting bit 15 of the

STATUS register ($40) to '1' and also by indicating a C-BUS interrupt request by pulling the IRQN pin low.

Note that on reset, the IRQENAB register ($1F) bit 15 will automatically be set to '1', thus enabling the

RDY interrupt to activate the IRQN pin. Refer also to section 6.1 for a description of the start-up sequence.

Connecting the ENABXTAL pin to VSS when the device is operational will force the device into a power-

save mode where the C-BUS interface and clock input (XTALIN) are disabled and the crystal oscillator is

powered down. However, the BIAS pin and C-BUS registers are not disturbed, so normal operation can be

resumed by re-connecting the ENABXTAL pin to IOVDD and waiting for the crystal oscillator to re-start.

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