PIC16LC554 datasheet(25/96 Pages) MICROCHIP

25 / 96 page

Preliminary

DS40143B-page 25

PIC16C55X(A)

5.2

PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The

corresponding data direction register is TRISB. A '1' in

the TRISB register puts the corresponding output driver

in a high impedance mode. A '0' in the TRISB register

puts the contents of the output latch on the selected

pin(s).

Reading PORTB register reads the status of the pins,

whereas writing to it will write to the port latch. All write

operations are read-modify-write operations. So a write

to a port implies that the port pins are ﬁrst read, then

this value is modiﬁed and written to the port data latch.

Each of the PORTB pins has a weak internal pull-up

(

≈200 µA typical). A single control bit can turn on all the

pull-ups. This

done

clearing

the

RBPU

(OPTION<7>) bit. The weak pull-up is automatically

turned off when the port pin is conﬁgured as an output.

The pull-ups are disabled on Power-on Reset.

Four of PORTB’s pins, RB7:RB4, have an interrupt on

change feature. Only pins conﬁgured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

conﬁgured as an output is excluded from the interrupt

on change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’ed together to generate the RBIF interrupt (ﬂag

latched in INTCON<0>).

FIGURE 5-3:

BLOCK DIAGRAM OF

RB7:RB4 PINS

Data Latch

From other

RBPU(2)

VDD

I/O

Data bus

WR PortB

WR TRISB

Set RBIF

TRIS Latch

RD TRISB

RD PortB

RB7:RB4 pins

weak

pull-up

RD Port

Latch

TTL

Input

Buffer

pin(1)

Note 1: I/O pins have diode protection to VDD and VSS.

Note 2: TRISB = 1 enables weak pull-up if RBPU = '0'

(OPTION<7>).

Buffer

RB7:RB6 in serial programming mode

This interrupt can wake the device from SLEEP. The

user, in the interrupt service routine, can clear the

interrupt in the following manner:

Any read or write of PORTB. This will end the

mismatch condition.

Clear ﬂag bit RBIF.

A mismatch condition will continue to set ﬂag bit RBIF.

Reading PORTB will end the mismatch condition, and

allow ﬂag bit RBIF to be cleared.

This interrupt on mismatch feature, together with

software conﬁgurable pull-ups on these four pins allow

easy interface to a key pad and make it possible for

wake-up on key-depression. (See AN552 in the

Microchip

Embedded Control Handbook.)

The interrupt on change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt on change

feature. Polling of PORTB is not recommended while

using the interrupt on change feature.

FIGURE 5-4:

BLOCK DIAGRAM OF

RB3:RB0 PINS

Note:

If a change on the I/O pin should occur when the

read operation is being executed (start of the Q2

cycle), then the RBIF interrupt ﬂag may not

get set.

Data Latch

RBPU(2)

VDD

Data bus

WR PortB

WR TRISB

RD TRISB

RD PortB

weak

pull-up

RD Port

RB0/INT

I/O

pin(1)

TTL

Input

Buffer

Note 1: I/O pins have diode protection to VDD and VSS.

Note 2: TRISB = 1 enables weak pull-up if RBPU = '0'

(OPTION<7>).

Buffer

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