PIC16LC554 datasheet(47/96 Pages) MICROCHIP

47 / 96 page

Preliminary

DS40143B-page 47

PIC16C55X(A)

7.6

Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users may wish to save key reg-

isters during an interrupt, e.g. W register and STATUS

Example 7-1 stores and restores the STATUS and W

registers. The user register, W_TEMP, must be deﬁned

in both banks and must be deﬁned at the same offset

from the bank base address (i.e., W_TEMP is deﬁned

at 0x20 in Bank 0 and it must also be deﬁned at 0xA0

in Bank 1). The user register, STATUS_TEMP, must be

deﬁned in Bank 0. The Example 7-1:

• Stores the W register

• Stores the STATUS register in Bank 0

• Executes the ISR code

• Restores the STATUS (and bank select bit

• Restores the W register

EXAMPLE 7-1:

SAVING THE STATUS AND

W REGISTERS IN RAM

MOVWF

W_TEMP

;copy W to temp register,

;could be in either bank

SWAPF

STATUS,W

;swap status to be saved into W

BCF

STATUS,RP0

;change to bank 0 regardless

;of current bank

MOVWF

STATUS_TEMP

;save status to bank 0

;register

(ISR)

SWAPF

STATUS_TEMP,W

;swap STATUS_TEMP register

;into W, sets bank to original

;state

MOVWF

STATUS

;move W into STATUS register

SWAPF

W_TEMP,F

;swap W_TEMP

SWAPF

W_TEMP,W

;swap W_TEMP into W

7.7

Watchdog Timer (WDT)

The watchdog timer is a free running on-chip RC oscil-

lator which does not require any external components.

This RC oscillator is separate from the RC oscillator of

the CLKIN pin. That means that the WDT will run, even

if the clock on the OSC1 and OSC2 pins of the device

has been stopped, for example, by execution of a

SLEEP

instruction. During normal operation, a WDT

time-out generates a device RESET. If the device is in

SLEEP mode, a WDT time-out causes the device to

wake-up and continue with normal operation. The WDT

can be permanently disabled by programming the con-

ﬁguration bit WDTE as clear (Section 7.1).

7.7.1

WDT PERIOD

The WDT has a nominal time-out period of 18 ms, (with

no prescaler). The time-out periods vary with tempera-

ture, VDD and process variations from part to part (see

DC specs). If longer time-out periods are desired, a

prescaler with a division ratio of up to 1:128 can be

assigned to the WDT under software control by writing

to the OPTION register. Thus, time-out periods up to

2.3 seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT

and the postscaler, if assigned to the WDT, and prevent

it from timing out and generating a device RESET.

The TO bit in the STATUS register will be cleared upon

a Watchdog Timer time-out.

7.7.2

WDT PROGRAMMING CONSIDERATIONS

It should also be taken in account that under worst case

conditions (VDD = Min., Temperature = Max., max.

WDT prescaler) it may take several seconds before a

WDT time-out occurs.

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