PIC16LC554 datasheet(49/96 Pages) MICROCHIP

49 / 96 page

Preliminary

DS40143B-page 49

PIC16C55X(A)

7.8

Power-Down Mode (SLEEP)

The Power-down mode is entered by executing a

SLEEP

instruction.

If enabled, the Watchdog Timer will be cleared but

keeps running, the PD bit in the STATUS register is

cleared, the TO bit is set, and the oscillator driver is

turned off. The I/O ports maintain the status they had,

before SLEEP was executed (driving high, low, or

hi-impedance).

For lowest current consumption in this mode, all I/O

pins should be either at VDD, or VSS, with no external

circuitry drawing current from the I/O pin. I/O pins that

are hi-impedance inputs should be pulled high or low

externally to avoid switching currents caused by ﬂoat-

ing inputs. The T0CKI input should also be at VDD or

VSS for lowest current consumption. The contribution

from on chip pull-ups on PORTB should be considered.

The MCLR pin must be at a logic high level (VIHMC).

7.8.1

WAKE-UP FROM SLEEP

The device can wake-up from SLEEP through one of

the following events:

External reset input on MCLR pin

Watchdog Timer Wake-up (if WDT was enabled)

Interrupt from RB0/INT pin or RB Port change

The ﬁrst event will cause a device reset. The two latter

events are considered a continuation of program exe-

cution. The TO and PD bits in the STATUS register can

be used to determine the cause of device reset.

bit, which is set on power-up is cleared when SLEEP is

invoked. TO bit is cleared if WDT Wake-up occurred.

When the SLEEP instruction is being executed, the

next instruction (PC + 1) is pre-fetched. For the device

to wake-up through an interrupt event, the correspond-

ing interrupt enable bit must be set (enabled). Wake-up

is regardless of the state of the GIE bit. If the GIE bit is

clear (disabled), the device continues execution at the

instruction after the SLEEP instruction. If the GIE bit is

set (enabled), the device executes the instruction after

the SLEEP instruction and then branches to the inter-

rupt address (0004h). In cases where the execution of

the instruction following SLEEP is not desirable, the

user should have an NOP after the SLEEP instruction.

The WDT is cleared when the device wakes-up from

sleep, regardless of the source of wake-up.

Note:

It should be noted that a RESET generated

by a WDT time-out does not drive MCLR

pin low.

Note:

If the global interrupts are disabled (GIE is

cleared), but any interrupt source has both

its interrupt enable bit and the correspond-

ing interrupt ﬂag bits set, the device will

immediately wakeup from sleep. The sleep

instruction is completely executed.

FIGURE 7-16: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q3 Q4

Q1 Q2

Q2 Q3 Q4

Q1 Q2 Q3 Q4

Q2 Q3

Q1 Q2

OSC1

CLKOUT(4)

INT pin

INTF ﬂag

(INTCON<1>)

GIE bit

(INTCON<7>)

INSTRUCTION FLOW

Instruction

fetched

Instruction

executed

PC+1

PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2

0004h

0005h

Dummy cycle

TOST(2)

PC+2

Note

XT, HS or LP oscillator mode assumed.

TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.

GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line.

CLKOUT is not available in these osc modes, but shown here for timing reference.

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