PIC16F84A datasheet(63/68 Pages) MICROCHIP

63 / 68 page

PIC16F84A

Preliminary

DS35007A-page 63

INDEX

Absolute Maximum Ratings ............................................... 41

AC (Timing) Characteristics ............................................... 47

Architecture, Block Diagram ................................................ 3

Assembler

MPASM Assembler .................................................... 37

Banking, Data Memory .................................................... 6, 8

CLKIN Pin ............................................................................ 4

CLKOUT Pin ........................................................................ 4

Code Protection ........................................................... 21, 32

Configuration Bits ............................................................... 21

Conversion Considerations ................................................ 59

Data EEPROM Memory ..................................................... 19

EEADR Register .................................................... 7, 24

EECON1 Register ............................................ 7, 19, 24

EECON2 Register ............................................ 7, 19, 24

EEDATA Register .................................................. 7, 24

Write Complete Enable (EEIE Bit) ....................... 10, 29

Write Complete Flag (EEIF Bit) ............................ 19, 29

Data EEPROM Write Complete ......................................... 29

Data Memory ....................................................................... 6

Bank Select (RP0 Bit) .............................................. 6, 8

Banking ........................................................................ 6

DC & AC Characteristics Graphs/Tables ........................... 53

DC Characteristics ........................................... 43, 44, 45, 46

Development Support ........................................................ 35

Development Tools ............................................................ 35

EECON1 Register .............................................................. 19

EEIF Bit ................................................................ 19, 29

RD Bit ......................................................................... 19

WR Bit ........................................................................ 19

WREN Bit ................................................................... 19

WRERR Bit ................................................................ 19

Electrical Characteristics .................................................... 41

Endurance ............................................................................ 1

Errata ................................................................................... 2

External Power-on Reset Circuit ........................................ 25

Firmware Instructions ......................................................... 33

ftp site ................................................................................ 65

Fuzzy Logic Dev. System (

fuzzyTECH

®-MP) ................... 37

I/O Ports ............................................................................. 13

ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 35

ID Locations ................................................................. 21, 32

In-Circuit Serial Programming (ICSP) .......................... 21, 32

Indirect Addressing ............................................................ 11

FSR Register ............................................... 6, 7, 11, 24

INDF Register ........................................................ 7, 24

Instruction Format .............................................................. 33

Instruction Set .................................................................... 33

Summary Table .......................................................... 34

INT Interrupt (RB0/INT) ...................................................... 29

INTCON Register ........................................ 7, 10, 18, 24, 28

EEIE Bit ............................................................... 10, 29

GIE Bit ........................................................... 10, 28, 29

INTE Bit ............................................................... 10, 29

INTF Bit ............................................................... 10, 29

RBIE Bit ............................................................... 10, 29

RBIF Bit ......................................................... 10, 15, 29

T0IE Bit ................................................................ 10, 29

T0IF Bit .......................................................... 10, 18, 29

Interrupt Sources ......................................................... 21, 28

Block Diagram ........................................................... 28

Data EEPROM Write Complete ........................... 28, 31

Interrupt on Change (RB7:RB4) ................ 4, 15, 28, 31

RB0/INT Pin, External ............................... 4, 16, 28, 31

TMR0 Overflow .................................................... 18, 28

Interrupts, Context Saving During ..................................... 29

Interrupts, Enable Bits

Data EEPROM Write Complete Enable

(EEIE Bit) ............................................................. 10, 29

Global Interrupt Enable (GIE Bit) ............................... 10

Interrupt on Change (RB7:RB4) Enable

(RBIE Bit) ................................................................... 10

RB0/INT Enable (INTE Bit) ........................................ 10

TMR0 Overflow Enable (T0IE Bit) ............................. 10

Interrupts, Flag Bits ........................................................... 28

Data EEPROM Write Complete Flag

(EEIF Bit) ............................................................. 19, 29

Interrupt on Change (RB7:RB4) Flag (RBIF Bit) ....... 10

RB0/INT Flag (INTF Bit) ............................................ 10

TMR0 Overflow Flag (T0IF Bit) .................................. 10

KeeLoq

® Evaluation and Programming Tools .................. 38

Master Clear (MCLR)

MCLR Pin .....................................................................4

MCLR Reset, Normal Operation ................................ 23

MCLR Reset, SLEEP .......................................... 23, 31

Memory Organization ...........................................................5

Data EEPROM Memory ............................................ 19

Data Memory ................................................................6

Program Memory ..........................................................5

Migration from Baseline to Midrange Devices ................... 62

MPLAB Integrated Development Environment

Software ............................................................................ 37

On-Line Support ................................................................ 65

OPCODE Field Descriptions ............................................. 33

OPTION_REG Register ................................. 7, 9, 16, 18, 24

INTEDG Bit ............................................................ 9, 29

PS2:PS0 Bits ......................................................... 9, 17

PSA Bit .................................................................. 9, 17

RBPU Bit ......................................................................9

T0CS Bit .......................................................................9

T0SE Bit .......................................................................9

OSC1 Pin ..............................................................................4

OSC2 Pin ..............................................................................4

Oscillator Configuration ............................................... 21, 22

HS ........................................................................ 22, 28

LP ........................................................................ 22, 28

RC ................................................................. 22, 23, 28

Selection (FOSC1:FOSC0 Bits) ................................ 21

XT ........................................................................ 22, 28

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