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PIC16F84A 数据表(PDF) 23 Page - Microchip Technology |
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PIC16F84A 数据表(HTML) 23 Page - Microchip Technology |
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23 / 68 page ![]() PIC16F84A © 1998 Microchip Technology Inc. Preliminary DS35007A-page 23 6.2.3 RC OSCILLATOR For timing insensitive applications the RC device option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) values, capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types also affects the oscillation frequency, especially for low Cext values. The user needs to take into account variation due to tolerance of the external R and C components. Figure 6-4 shows how an R/C combination is connected to the PIC16F84A. FIGURE 6-4: RC OSCILLATOR MODE 6.3 Reset The PIC16F84A differentiates between various kinds of reset: • Power-on Reset (POR) • MCLR reset during normal operation • MCLR reset during SLEEP • WDT Reset (during normal operation) • WDT Wake-up (during SLEEP) Figure 6-5 shows a simplified block diagram of the on-chip reset circuit. The MCLR reset path has a noise filter to ignore small pulses. The electrical specifica- tions state the pulse width requirements for the MCLR pin. Some registers are not affected in any reset condition; their status is unknown on a POR reset and unchanged in any other reset. Most other registers are reset to a “reset state” on POR, MCLR or WDT reset during normal operation and on MCLR reset during SLEEP. They are not affected by a WDT reset during SLEEP, since this reset is viewed as the resumption of normal operation. Table 6-3 gives a description of reset conditions for the program counter (PC) and the STATUS register. Table 6-4 gives a full description of reset states for all registers. The TO and PD bits are set or cleared differently in dif- ferent reset situations (Section 6.7). These bits are used in software to determine the nature of the reset. FIGURE 6-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT OSC2/CLKOUT Cext Rext PIC16FXX OSC1 Fosc/4 Internal clock VDD VSS Recommended values: 5 k Ω ≤ Rext ≤ 100 kΩ Cext > 20pF S R Q External Reset MCLR VDD OSC1/ WDT Module VDD rise detect OST/PWRT On-chip RC OSC(1) WDT Time_Out Power_on_Reset OST 10-bit Ripple counter PWRT Chip_Reset 10-bit Ripple counter Reset Enable OST Enable PWRT SLEEP CLKIN Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. See Table 6-5 |
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