PIC16F84A datasheet(11/68 Pages) MICROCHIP

11 / 68 page

PIC16F84A

Preliminary

DS35007A-page 11

2.3

PCL and PCLATH

The program counter (PC) speciﬁes the address of the

instruction to fetch for execution. The PC is 13 bits

wide. The low byte is called the PCL register. This reg-

ister is readable and writable. The high byte is called

the PCH register. This register contains the PC<12:8>

bits and is not directly readable or writable. All updates

to the PCH register go through the PCLATH register.

2.3.1

STACK

The stack allows a combination of up to 8 program calls

and interrupts to occur. The stack contains the return

address from this branch in program execution.

Midrange devices have an 8 level deep x 13-bit wide

hardware stack. The stack space is not part of either

program or data space and the stack pointer is not

readable or writable. The PC is PUSHed onto the stack

when a CALL instruction is executed or an interrupt

causes a branch. The stack is POPed in the event of a

RETURN,

RETLW

or a RETFIE instruction execution.

PCLATH is not modiﬁed when the stack is PUSHed or

POPed.

After the stack has been PUSHed eight times, the ninth

push overwrites the value that was stored from the ﬁrst

push. The tenth push overwrites the second push (and

so on).

2.4

Indirect Addressing; INDF and FSR

Registers

The INDF register is not a physical register. Address-

ing INDF actually addresses the register whose

address is contained in the FSR register (FSR is a

pointer). This is indirect addressing.

EXAMPLE 2-1:

INDIRECT ADDRESSING

• Register ﬁle 05 contains the value 10h

• Register ﬁle 06 contains the value 0Ah

• Load the value 05 into the FSR register

• A read of the INDF register will return the value of

10h

• Increment the value of the FSR register by one

(FSR = 06)

• A read of the INDF register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce

00h. Writing to the INDF register indirectly results in a

no-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 20h-2Fh

using indirect addressing is shown in Example 2-2.

EXAMPLE 2-2:

HOW TO CLEAR RAM

USING INDIRECT

ADDRESSING

movlw

0x20

;initialize pointer

movwf

FSR

;

to RAM

clrf

INDF

;clear INDF register

incf

FSR

;inc pointer

btfss

FSR,4 ;all done?

goto

;NO, clear next

CONTINUE

;YES, continue

An effective 9-bit address is obtained by concatenating

the 8-bit FSR register and the IRP bit (STATUS<7>), as

shown in Figure 2-1. However, IRP is not used in the

PIC16F84A.

PIC16F84A 数据表(PDF) 11 Page - Microchip Technology

PIC16F84A 数据表(HTML) 11 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

数据表下载