PIC16F84A datasheet(20/68 Pages) MICROCHIP

20 / 68 page

PIC16F84A

DS35007A-page 20

Preliminary

5.1

Reading the EEPROM Data Memory

To read a data memory location, the user must write the

address to the EEADR register and then set control bit

RD (EECON1<0>). The data is available, in the very

next cycle, in the EEDATA register; therefore it can be

read in the next instruction. EEDATA will hold this value

until another read or until it is written to by the user

(during a write operation).

EXAMPLE 5-1:

DATA EEPROM READ

BCF

STATUS, RP0

; Bank 0

MOVLW

CONFIG_ADDR

;

MOVWF

EEADR

; Address to read

BSF

STATUS, RP0

; Bank 1

BSF

EECON1, RD

; EE Read

BCF

STATUS, RP0

; Bank 0

MOVF

EEDATA, W

; W = EEDATA

5.2

Writing to the EEPROM Data Memory

To write an EEPROM data location, the user must ﬁrst

write the address to the EEADR register and the data

to the EEDATA register. Then the user must follow a

speciﬁc sequence to initiate the write for each byte.

EXAMPLE 5-1:

DATA EEPROM WRITE

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. We strongly

recommend that interrupts be disabled during this

code segment.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will

be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. EEIF must be

cleared by software.

5.3

Write Verify

Depending on the application, good programming prac-

tice may dictate that the value written to the Data

EEPROM should be veriﬁed (Example 5-1) to the

desired value to be written. This should be used in

applications where an EEPROM bit will be stressed

near the speciﬁcation limit. The Total Endurance disk

will help determine your comfort level.

Generally the EEPROM write failure will be a bit which

was written as a '0', but reads back as a '1' (due to

leakage off the bit).

EXAMPLE 5-1:

WRITE VERIFY

BCF

STATUS, RP0 ; Bank 0

; Any code can go here

;

MOVF

EEDATA, W

; Must be in Bank 0

BSF

STATUS, RP0 ; Bank 1

READ

BSF

EECON1, RD

; YES, Read the

;

value written

BCF

STATUS, RP0 ; Bank 0

;

; Is the value written (in W reg) and

;

read (in EEDATA) the same?

;

SUBWF EEDATA, W

;

BTFSS STATUS, Z

; Is difference 0?

GOTO

WRITE_ERR

; NO, Write error

; YES, Good write

; Continue program

TABLE 5-1

REGISTERS/BITS ASSOCIATED WITH DATA EEPROM

BSF

STATUS, RP0

; Bank 1

BCF

INTCON, GIE

; Disable INTs.

BSF

EECON1, WREN ; Enable Write

MOVLW

55h

;

MOVWF

EECON2

; Write 55h

MOVLW

AAh

;

MOVWF

EECON2

; Write AAh

BSF

EECON1,WR

; Set WR bit

;

begin write

BSF

INTCON, GIE

; Enable INTs.

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

Power-on

Reset

Value on all

other resets

08h

EEDATA

EEPROM data register

xxxx xxxx

uuuu uuuu

09h

EEADR

EEPROM address register

xxxx xxxx

uuuu uuuu

88h

EECON1

—

EEIF

WRERR

WREN

---0 x000

---0 q000

89h

EECON2

EEPROM control register 2

---- ----

Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends upon condition. Shaded cells are not

used by data EEPROM.

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