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PIC16F84A 数据表(PDF) 7 Page - Microchip Technology |
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PIC16F84A 数据表(HTML) 7 Page - Microchip Technology |
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7 / 68 page  PIC16F84A © 1998 Microchip Technology Inc. Preliminary DS35007A-page 7 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (Figure 2-1 and Table 2-1) are used by the CPU and Peripheral functions to control the device operation. These registers are static RAM. The special function registers can be classified into two sets, core and peripheral. Those associated with the core functions are described in this section. Those related to the operation of the peripheral features are described in the section for that specific feature. TABLE 2-1 REGISTER FILE SUMMARY Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on Power-on Reset Value on all other resets (Note3) Bank 0 00h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ---- 01h TMR0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h PCL Low order 8 bits of the Program Counter (PC) 0000 0000 0000 0000 03h STATUS (2) IRP RP1 RP0 TO PD ZDC C 0001 1xxx 000q quuu 04h FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu 05h PORTA (4) — — — RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu 06h PORTB (5) RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT xxxx xxxx uuuu uuuu 07h Unimplemented location, read as '0' ---- ---- ---- ---- 08h EEDATA EEPROM data register xxxx xxxx uuuu uuuu 09h EEADR EEPROM address register xxxx xxxx uuuu uuuu 0Ah PCLATH — — — Write buffer for upper 5 bits of the PC (1) ---0 0000 ---0 0000 0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u Bank 1 80h INDF Uses contents of FSR to address data memory (not a physical register) ---- ---- ---- ---- 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h PCL Low order 8 bits of Program Counter (PC) 0000 0000 0000 0000 83h STATUS (2) IRP RP1 RP0 TO PD ZDC C 0001 1xxx 000q quuu 84h FSR Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu 85h TRISA — — — PORTA data direction register ---1 1111 ---1 1111 86h TRISB PORTB data direction register 1111 1111 1111 1111 87h Unimplemented location, read as '0' ---- ---- ---- ---- 88h EECON1 — — — EEIF WRERR WREN WR RD ---0 x000 ---0 q000 89h EECON2 EEPROM control register 2 (not a physical register) ---- ---- ---- ---- 0Ah PCLATH — — — Write buffer for upper 5 bits of the PC (1) ---0 0000 ---0 0000 0Bh INTCON GIE EEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u Legend: x = unknown, u = unchanged. - = unimplemented read as '0', q = value depends on condition. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a slave register for PC<12:8>. The contents of PCLATH can be transferred to the upper byte of the program counter, but the contents of PC<12:8> is never transferred to PCLATH. 2: The TO and PD status bits in the STATUS register are not affected by a MCLR reset. 3: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 4: On any device reset, these pins are configured as inputs. 5: This is the value that will be in the port output latch. |
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