MEC1322 datasheet(104/456 Pages) MICROCHIP

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MEC1322

DS00001719D-page 104

 2014 - 2015 Microchip Technology Inc.

7.3

Terminology

7.3.1

ARM IP TERMS AND ACRONYMS

•Cortex-M4F

• The ARM designation for the specific IP selected for this product: a Cortex M4 processor core containing a hard-

ware Floating Point Unit (FPU).

•ARMv7

• The identifying name for the general architecture implemented by the Cortex-M family of IP products.

• Note that ARMv7 has no relationship to the older “ARM 7” product line, which is classified as an “ARMv3” archi-

tecture, and is very different.

•FPU

• Floating-Point Unit: a subblock included in the Core for implementing the Floating Point instruction set in hard-

ware.

•NVIC

• Nested Vectored Interrupt Controller subblock. Accepts external interrupt inputs. See documents ARM Limited:

ARM®v7-M Architecture Reference Manual, DDI0403D, November 2010 and ARM® Generic Interrupt Controller

Architecture version 1.0 Architecture Specification, IHI0048A, September 2008.

•FPB

• FLASH Patch Breakpoint subblock. Provides either Remapping (Address substitution) or Breakpointing (Excep-

tion or Halt) for a set of Instruction addresses and Data addresses. See Section 8.3 of ARM Limited: Cortex®-M4

Technical Reference Manual, DDI0439C, 29 June 2010.

• DAP

• Debug Access Port, a subblock consisting of DP and AP subblocks

•DP

• Any of the ports in the DAP subblock for connection to an off-chip Debugger. A single SWJ-DP option is currently

selected for this function, providing JTAG connectivity.

•SWJ-DP

•Serial Wire / JTAG Debug Port, the DP option selected by Microchip for the DAP.

•AP

• Any of the ports on the DAP subblock for accessing on-chip resources on behalf of the Debugger, independent of

processor operations. A single AHB-AP option is currently selected for this function.

•AHB-AP

• AHB Access Port, the AP option selected by Microchip for the DAP.

•MEM-AP

• A generic term for an AP that connects to a memory-mapped bus on-chip. For this product, this term is synony-

mous with the AHB Access Port, AHB-AP.

• ROM Table

• A ROM-based data structure in the Debug section that allows an external Debugger and/or a FW monitor to deter-

mine which of the Debug features are present.

•DWT

• Data Watchdog and Trace subblock. This contains comparators and counters used for data watchpoints and Core

activity tracing.

•ETM

• Embedded Trace Macrocell subblock. Provides enhancements for Trace output reporting, mostly from the DWT

subblock. It adds enhanced instruction tracing, filtering, triggering and timestamping.

•ITM

• Instrumentation Trace Macrocell subblock. Provides a HW Trace interface for “printf”-style reports from instru-

mented firmware builds, with timestamping also provided.

•TPIU

• Trace Port Interface Unit subblock. Multiplexes and buffers Trace reports from the ETM and ITM subblocks.

•TPA

• Trace Port Analyzer: any off-chip device that uses the TPIU output.

•ATB

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