STM32F756VG datasheet(121/228 Pages) STMICROELECTRONICS

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DocID027589 Rev 4

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STM32F756xx

Electrical characteristics

196

APB2

(up to

108 MHz)

TIM1

25.2

23.9

20.4

µA/MHz

TIM8

25.3

20.4

USART1

10.3

9.8

8.2

USART6

10.1

9.7

8.1

ADC1(5)

4.5

4.4

3.5

ADC2(5)

4.5

4.4

3.5

ADC3(5)

4.5

4.4

3.3

SDMMC1

8.5

7.9

6.7

SPI1/I2S1(3)

3.1

2.5

SPI4

3.1

2.5

SYSCFG

1.5

1.4

TIM9

8.8

8.4

6.9

TIM10

5.6

5.2

4.3

TIM11

5.4

5.2

4.3

SPI5

2.8

2.2

SPI6

2.8

2.2

SAI1

3.4

3.3

2.6

SAI2

3.3

3.2

2.5

LTDC

56.7

53.8

45.7

1. When the I/O compensation cell is ON, IDD typical value increases by 0.22 mA.

2. The BusMatrix is automatically active when at least one master is ON.

3. To enable an I2S peripheral, first set the I2SMOD bit and then the I2SE bit in the SPI_I2SCFGR register.

4. When the DAC is ON and EN1/2 bits are set in DAC_CR register, add an additional power consumption of

0.75 mA per DAC channel for the analog part.

5. When the ADC is ON (ADON bit set in the ADC_CR2 register), add an additional power consumption of

1.73 mA per ADC for the analog part.

Table 35. Peripheral current consumption (continued)

Peripheral

IDD(Typ)(1)

Unit

Scale 1

Scale 2

Scale 3

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