STM32F756VG datasheet(38/228 Pages) STMICROELECTRONICS

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Functional overview

STM32F756xx

38/228

DocID027589 Rev 4

2.25

Serial peripheral interface (SPI)/inter- integrated sound

interfaces (I2S)

The devices feature up to six SPIs in slave and master modes in full-duplex and simplex

communication modes. SPI1, SPI4, SPI5, and SPI6 can communicate at up to 50 Mbits/s,

SPI2 and SPI3 can communicate at up to 25 Mbit/s. The 3-bit prescaler gives 8 master

mode frequencies and the frame is configurable from 4 to 16 bits. The SPI interfaces

support NSS pulse mode, TI mode and Hardware CRC calculation. All SPIs can be served

by the DMA controller.

Three standard I2S interfaces (multiplexed with SPI1, SPI2 and SPI3) are available. They

can be operated in master or slave mode, in simplex communication modes, and can be

configured to operate with a 16-/32-bit resolution as an input or output channel. Audio

sampling frequencies from 8 kHz up to 192 kHz are supported. When either or both of the

I2S interfaces is/are configured in master mode, the master clock can be output to the

external DAC/CODEC at 256 times the sampling frequency.

All I2Sx can be served by the DMA controller.

2.26

Serial audio interface (SAI)

The devices embed two serial audio interfaces.

The serial audio interface is based on two independent audio subblocks which can operate

as transmitter or receiver with their FIFO. Many audio protocols are supported by each

block: I2S standards, LSB or MSB-justified, PCM/DSP, TDM, AC’97 and SPDIF output,

supporting audio sampling frequencies from 8 kHz up to 192 kHz. Both subblocks can be

configured in master or in slave mode.

In master mode, the master clock can be output to the external DAC/CODEC at 256 times of

the sampling frequency.

The two sub-blocks can be configured in synchronous mode when full-duplex mode is

required.

Smartcard mode

Single-wire half-duplex communication

IrDA SIR ENDEC block

LIN mode

Dual clock domain

Receiver timeout interrupt

Modbus communication

Auto baud rate detection

Driver Enable

1. X: supported.

Table 8. USART implementation (continued)

features(1)

USART1/2/3/6

UART4/5/7/8

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