STM32F756VG datasheet(41/228 Pages) STMICROELECTRONICS

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STM32F756xx

Functional overview

2.32

Controller area network (bxCAN)

The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to 1

Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as

extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive

FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one

CAN is used). 256 bytes of SRAM are allocated for each CAN.

2.33

Universal serial bus on-the-go full-speed (OTG_FS)

The device embeds an USB OTG full-speed device/host/OTG peripheral with integrated

transceivers. The USB OTG FS peripheral is compliant with the USB 2.0 specification and

with the OTG 2.0 specification. It has software-configurable endpoint setting and supports

suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is

generated by a PLL connected to the HSE oscillator.

The major features are:

•

Combined Rx and Tx FIFO size of 1.28 Kbytes with dynamic FIFO sizing

•

Support of the session request protocol (SRP) and host negotiation protocol (HNP)

•

1 bidirectional control endpoint + 5 IN endpoints + 5 OUT endpoints

•

12 host channels with periodic OUT support

•

Software configurable to OTG1.3 and OTG2.0 modes of operation

•

USB 2.0 LPM (Link Power Management) support

•

Internal FS OTG PHY support

•

HNP/SNP/IP inside (no need for any external resistor)

For OTG/Host modes, a power switch is needed in case bus-powered devices are

connected

2.34

Universal serial bus on-the-go high-speed (OTG_HS)

The device embeds a USB OTG high-speed (up to 480 Mb/s) device/host/OTG peripheral.

The USB OTG HS supports both full-speed and high-speed operations. It integrates the

transceivers for full-speed operation (12 MB/s) and features a UTMI low-pin interface (ULPI)

for high-speed operation (480 MB/s). When using the USB OTG HS in HS mode, an

external PHY device connected to the ULPI is required.

The USB OTG HS peripheral is compliant with the USB 2.0 specification and with the OTG

2.0 specification. It has software-configurable endpoint setting and supports

suspend/resume. The USB OTG controller requires a dedicated 48 MHz clock that is

generated by a PLL connected to the HSE oscillator.

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