STM32F756VG datasheet(36/228 Pages) STMICROELECTRONICS

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Functional overview

STM32F756xx

36/228

DocID027589 Rev 4

2.23

Inter-integrated circuit interface (I2C)

The device embeds 4 I2C. Refer to Table 7: I2C implementation for the features

implementation.

The I2C bus interface handles communication between the microcontroller and the serial

I2C bus. It controls all I2C bus-specific sequencing, protocol, arbitration and timing.

The I2C peripheral supports:

•

I2C-bus specification and user manual rev. 5 compatibility:

–

Slave and master modes, multimaster capability

–

Standard-mode (Sm), with a bitrate up to 100 kbit/s

–

Fast-mode (Fm), with a bitrate up to 400 kbit/s

–

7-bit and 10-bit addressing mode, multiple 7-bit slave addresses

–

Programmable setup and hold times

–

Optional clock stretching

•

System Management Bus (SMBus) specification rev 2.0 compatibility:

–

Hardware PEC (Packet Error Checking) generation and verification with ACK

control

–

Address resolution protocol (ARP) support

–

SMBus alert

•

Power System Management Protocol (PMBusTM) specification rev 1.1 compatibility

•

Independent clock: a choice of independent clock sources allowing the I2C

communication speed to be independent from the PCLK reprogramming.

•

Programmable analog and digital noise filters

•

1-byte buffer with DMA capability

Table 7. I2C implementation

I2C features(1)

1. X: supported

I2C1

I2C2

I2C3

I2C4

Standard-mode (up to 100 kbit/s)

Fast-mode (up to 400 kbit/s)

Programmable analog and digital noise filters

SMBus/PMBus hardware support

Independent clock

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