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STM32F756VG 数据表(PDF) 187 Page - STMicroelectronics

部件名 STM32F756VG
功能描述  Up to 25 communication interfaces
PDF  228 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STM32F756VG 数据表(HTML) 187 Page - STMicroelectronics

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STM32F756xx
Electrical characteristics
196
SDRAM waveforms and timings
•
CL = 30 pF on data and address lines. CL = 10 pF on FMC_SDCLK unless otherwise
specified.
In all timing tables, the THCLK is the HCLK clock period.
–
For 3.0 V
≤VDD≤3.6 V, maximum FMC_SDCLK= 100 MHz at CL=20 pF (on
FMC_SDCLK).
–
For 2.7 V
≤VDD≤3.6 V, maximum FMC_SDCLK = 90 MHz at CL=30 pF (on
FMC_SDCLK).
–
For 1.71 V
≤VDD<1.9 V, maximum FMC_SDCLK = 70 MHz at CL=10 pF (on
FMC_SDCLK).
Figure 70. SDRAM read access waveforms (CL = 1)



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