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STM32F756VG 数据表(PDF) 193 Page - STMicroelectronics |
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STM32F756VG 数据表(HTML) 193 Page - STMicroelectronics |
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193 / 228 page  DocID027589 Rev 4 193/228 STM32F756xx Electrical characteristics 196 Figure 74. DCMI timing diagram 5.3.30 LCD-TFT controller (LTDC) characteristics Unless otherwise specified, the parameters given in Table 109 for LCD-TFT are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage summarized in Table 17, with the following configuration: • LCD_CLK polarity: high • LCD_DE polarity : low • LCD_VSYNC and LCD_HSYNC polarity: high • Pixel formats: 24 bits Table 109. LTDC characteristics (1) 1. Guaranteed by characterization results. Symbol ParameterMin Max Unit fCLK LTDC clock output frequency - 45 MHz DCLK LTDC clock output duty cycle 45 55 % tw(CLKH) tw(CLKL) Clock High time, low time tw(CLK)/2 − 0.5 tw(CLK)/2+0.5 ns tv(DATA) Data output valid time - 6 th(DATA) Data output hold time 2 - tv(HSYNC) HSYNC/VSYNC/DE output valid time -3 tv(VSYNC) tv(DE) th(HSYNC) HSYNC/VSYNC/DE output hold time 0.5 - th(VSYNC) th(DE) |
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