ADN2913

Data Sheet

Rev. A | Page 14 of 37

REGISTER MAP

Writing to register bits other than those labeled in Table 7 is not recommended and may cause unintended results.

Table 7. Internal Register Map1

Reg Name

R/W

Addr

(Hex)

Default

(Hex)

D7

D6

D5

D4

D3

D2

D1

D0

Readback/Status

FREQMEAS0

R

0x0

X

FREQ0[7:0] (RATE_FREQ[7:0])

FREQMEAS1

R

0x1

X

FREQ1[7:0] (RATE_FREQ[15:8])

FREQMEAS2

R

0x2

X

FREQ2[7:0] (RATE_FREQ[23:16])

FREQ_RB1

R

0x4

X

VCOSEL[7:0]

FREQ_RB2

R

0x5

X

X

FULLRATE

DIVRATE[3:0]

VCOSEL[9:8]

STATUSA

R

0x6

X

X

X

LOS

status

LOL

status

LOS done

Static LOL

X

RATE_

MEAS_

COMP

General Control

CTRLA

R/W

0x8

0x10

0

CDR_MODE[2:0]

0

Reset static

LOL

RATE_

MEAS_

EN

RATE_

MEAS_

RESET

CTRLB

R/W

0x9

0x00

SOFTWARE_

RESET

INIT_

FREQ_

ACQ

CDR

bypass

LOL_

CONFIG

LOS_PDN

LOS

polarity

0

0

CTRLC

R/W

0xA

0x05

0

0

0

0

0

REFCLK_

PDN

0

1

FLL Control

LTR_MODE

R/W

0xF

0x00

0

LOL data

FREF_RANGE[1:0]

DATA_TO_REF_RATIO[3:0]

D/PLL Control

DPLLA

R/W

0x10

0x1C

0

0

0

EDGE_SEL[1:0]

TRANBW[2:0]

DPLLD

R/W

0x13

0x06

0

0

0

0

0

ADAPTIVE_

SLICE_EN

DLL_SLEW[1:0]

Phase

R/W

0x14

0x00

0

0

0

0

SAMPLE_PHASE[3:0]

Slice

W

0x15

X

Extended

slice

Slice[6:0]

LA_EQ

R/W

0x16

0x08

RX_TERM_

FLOAT

INPUT_SEL[1:0]

ADAPTIVE_

EQ_EN

EQ_BOOST[3:0]

Slice

Readback

R

0x73

X

SLICE_RB[7:0]

Output Control

OUTPUTA

R/W

0x1E

0x00

0

0

Data

squelch

DATOUT_

DISABLE

CLKOUT_

DISABLE

DDR_

DISABLE

DATA_

POLARITY

CLOCK_

POLARITY

OUTPUTB

R/W

0x1F

0xCC

DATA_SWING[3:0]

CLOCK_SWING[3:0]

LOS Control

LOS_DATA

R/W

0x36

0x00

LOS_DATA[7:0]

LOS_CTRL

R/W

0x74

0x00

0

0

LOS_

WRITE

LOS_

ENABLE

LOS_

RESET

LOS_ADDRESS[2:0]

LOS_THRESH

R/W

0x38

0x0A

LOS_THRESHOLD[7:0]

PRBS Control

PRBS Gen 1

R/W

0x39

0x00

0

0

DATA_

CID_BIT

DATA_

CID_EN

0

DATA_

GEN_EN

DATA_GEN_MODE[1:0]

PRBS Gen 2

R/W

0x3A

0x00

DATA_CID_LENGTH[7:0]

PRBS Gen 3

R/W

0x3B

0x00

PROG_DATA[7:0]

PRBS Gen 4

R/W

0x3C

0x00

PROG_DATA[15:8]

PRBS Gen 5

R/W

0x3D

0x00

PROG_DATA[23:16]

PRBS Gen 6

R/W

0x3E

0x00

PROG_DATA[31:24]

PRBS Rec 1

R/W

0x3F

0x00

0

0

0

0

DATA_

RECEIVER_

CLEAR

DATA_

RECEIVER_

ENABLE

DATA_RECEIVER_

MODE[1:0]

PRBS Rec 2

R

0x40

0x00

PRBS_ERROR_COUNT[7:0]

PRBS Rec 3

R

0x41

0x00

X

X

X

X

X

X

X

PRBS_

ERROR

PRBS Rec 4

R

0x42

X

DATA_LOADED[7:0]