ADN2913 datasheet(28/37 Pages) AD

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ADN2913

Data Sheet

Rev. A | Page 28 of 37

Using the Reference Clock to Measure Data Frequency

The user can also provide a reference clock to measure the

recovered data frequency. In this case, the ADN2913 compares

the frequency of the incoming data to the incoming reference

clock and returns a ratio of the two frequencies to 0.01%

(100 ppm). The accuracy error of the reference clock is added to

the accuracy error of the ADN2913 data rate measurement. For

example, if a 100 ppm accuracy reference clock is used, the total

accuracy of the measurement is 200 ppm.

The reference clock can range from 11.05 MHz to 176.8 MHz.

Prior to reading back the data rate using the reference clock, the

FREF_RANGE[1:0] bits (Bits[D5:D4] in Register 0xF) must be

set to the appropriate frequency range with respect to the reference

clock being used, according to Table 24. A fine data rate readback is

then executed as follows:

Apply the reference clock.

Write a 0 to REFCLK_PDN (Bit D2 in Register 0xA) to

enable the reference clock circuit.

Write to FREF_RANGE[1:0] (Bits[D5:D4] in Register 0xF)

to select the appropriate reference clock frequency circuit.

Write a 1 to RATE_MEAS_EN (Bit D1 in Register 0x8). This

enables the fine data rate measurement capability of the

ADN2913. This bit is level sensitive and does not need to be

reset to perform subsequent frequency measurements.

Write a low to high to low transition to RATE_MEAS_

RESET (Bit D0 in Register 0x8). This initiates a new data

rate measurement.

Read back RATE_MEAS_COMP (Bit D0 in Register 0x6). If

the bit is 0, the measurement is not complete. If it is 1, the

measurement is complete and the data rate can be read

back on RATE_FREQ[23:0], FULLRATE, and

DIVRATE[3:0] (see Table 7). The approximate time for a

data rate measurement is given in Equation 2.

Use the following equation to determine the data rate:

]

DIVRATE[

FULLRATE

]

LTR[

REFLCLK

DATARATE

]

FREQ[

RATE

)

(





(1)

where:

fDATARATE

is the data rate (Mbps).

RATE_FREQ[23:0]

is from FREQ2[7:0] (most significant byte),

FREQ1[7:0], and FREQ0[7:0] (least significant byte). See Table 7.

fREFCLK

is the reference clock frequency (MHz).

FULLRATE

= FREQ_RB2[6].

DIVRATE[3:0]

= FREQ_RB2[5:2].

MSB

LSB

D23 to D16

D15 to D8

D7 to D0

FREQ2[7:0]

FREQ1[7:0]

FREQ0[7:0]

Consider the example of a 1.25 Gbps (GbE) input signal and a

reference clock source of 32 MHz at the PIN/NIN and REFCLKP/

REFCLKN ports, respectively. In this case, FREF_RANGE[1:0]

(Bits[D5:D4] in Register 0xF) = 01 and the reference frequency

falls into the range of 22.1 MHz to 44.2 MHz.

After following Step 1 through Step 6, the readback value of

RATE_FREQ[23:0] is 0x13880, which is equal to 8 × 104. The

readback value of FULLRATE (Bit D6 in Register 0x5) is 1, and

the readback value of DIVRATE[3:0] (Bits[D5:D2] in Register

0x5) is 2. Inserting these values into Equation 1 yields

((8 × 104) × (32 × 106))/(21 × 27 × 21 × 22) = 1.25 Gbps

If subsequent frequency measurements are required, keep

RATE_MEAS_EN (Bit D1 in Register 0x8) set to 1. It does not

need to be reset. The measurement process is reset by writing a

1 followed by a 0 to RATE_MEAS_RESET (Bit D0 in Register 0x8).

This initiates a new data rate measurement. Follow Step 2

through Step 6 to read back the new data rate. Note that a data

rate readback is valid only if the LOL pin is low. If LOL is high,

the data rate readback is invalid.

Initiating a frequency measurement by writing a low to high to

low transition into RATE_MEAS_RESET (Bit D0 in Register 0x8)

also resets the RATE_MEAS_COMP bit (Bit D0 in Register 0x6).

The approximate time to complete a frequency measurement from

RATE_MEAS_RESET being written with a low to high to low

transition to when the RATE_MEAS_COMP bit returns high is

given by

REFCLK

LTR

Time

Measuremen

]

[

2 



(2)

LOS Configuration

The LOS detector output, LOS (Pin 5), can be configured to

be either active high or active low. If LOS polarity (Bit 2 in

high when a loss of signal condition is detected.

ADDITIONAL FEATURES AVAILABLE VIA THE I2C

INTERFACE

Coarse Data Rate Readback

The data rate can be read back over the I2C interface to approx-

imately ±5% without using an external reference clock according to

the following formula:

]

DIVRATE[

FULLRATE

DCO

Data





(3)

where

FULLRATE

= FREQ_RB2[6].

DIVRATE[3:0]

= FREQ_RB2[5:2].

fDCO

is the frequency of the DCO, derived as shown in Table 25.

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