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ADN2913

Data Sheet

Rev. A | Page 22 of 37

FUNCTIONAL DESCRIPTION

FREQUENCY ACQUISITION

The ADN2913 acquires the frequency from the input data over

a range of data frequencies from 6.5 Mbps to 8.5 Gbps. The lock

detector circuit compares the frequency of the DCO and the

frequency of the incoming data. When these frequencies differ by

more than 1000 ppm, the LOL pin is asserted and a new frequency

acquisition cycle is initiated. The DCO frequency is reset to the

lowest point of the range, and the internal division rate is set to

the lowest value of N = 1, which is the highest octave of data rates.

The frequency detector then compares this sampling rate frequency

to the data rate frequency and either increases N by a factor of 2

if the sampling rate frequency is greater than the data rate

frequency, or increases the DCO frequency if the data rate

frequency is greater than the sampling rate frequency. Initially,

the DCO frequency is incremented in large steps to aid fast

acquisition. As the DCO frequency approaches the data frequency,

the step size is reduced until the DCO frequency is within 250

ppm of the data frequency, at which point LOL is deasserted.

When LOL is deasserted, the frequency-locked loop is turned

off. The PLL or DLL pulls in the DCO frequency until the DCO

frequency equals the data frequency.

LIMITING AMPLIFIER

The limiting amplifier has differential inputs (PIN and NIN)

that are each internally terminated with 50 Ω to an on-chip

voltage reference (VCM = 0.95 V typically). The inputs must be

ac-coupled. Input offset is factory trimmed to achieve better

than 10 mV p-p typical sensitivity with minimal drift. The

limiting amplifier can be driven differentially or single-ended.

DC coupling of the limiting amplifier is not possible because

the user must supply a common-mode voltage to exactly match

the internal common-mode voltage; otherwise, the internal

50 Ω termination resistors absorb the difference in common-

mode voltages.

Another reason that the limiting amplifier cannot be dc-coupled is

that the factory trimmed input offset becomes invalid. The offset is

adjusted to zero by differential currents from the slice adjust DAC

(see Figure 1). With ac coupling, all of the current goes to the 50 Ω

termination resistors on the ADN2913. However, with dc coupling,

this current is shared with the external drive circuit, and calibration

of the offset is lost. In addition, the slice adjust must have all the

current from the slice adjust DAC go to the resistors; otherwise,

the calibration is lost (see the Slice Adjust section).

SLICE ADJUST

The quantizer slicing level can be offset by ±100 mV in 1.6 mV

steps or by ±15 mV in 0.24 mV steps to mitigate the effect of

amplified spontaneous emission (ASE) noise or duty cycle

distortion. The quantizer slice adjust level is set by the slice[6:0]

bits in Register 0x15.

Accurate control of the slice threshold requires the user to read

back the factory trimmed offset, which is stored as a 7-bit

number in the slice readback register (Register 0x73). Use

Table 20 to decode the measured offset of the device, where an

LSB corresponds to 0.24 mV.

Table 20. Program Slice Level, Normal Slice Mode

(Extended Slice = 0)

Slice[6:0]

Decimal Value

Offset

0000000

Slice function disabled

0000001

−15 mV

…

1000000

0 mV

…

1111111

127

+14.75 mV

The amount of offset required for manual slice adjustment is

determined by subtracting the offset of the device from the

desired slice adjust level. Use Table 20 or Table 21 to determine

the code word to be written to the slice register.

An extended slice with coarser granularity for each LSB step is

found in Table 21. Setting the extended slice bit (Bit 7) = 1 in

factor of 6.

Table 21. Program Slice Level, Extended Slice Mode

(Extended Slice = 1)

Slice[6:0]

Decimal Value

Offset

0000000

128

Slice function disabled

0000001

129

−100 mV

…

1000000

192

0 mV

…

1111111

255

+100 mV

When manual slice is desired, disable the dc offset loop, which

drives duty cycle distortion on the data to 0. Adaptive slice is

disabled by setting ADAPTIVE_SLICE_EN = 0 in Register 0x13.

EDGE SELECT

A binary, or Alexander phase, detector drives both the DLL and

PLL at all division rates. Duty cycle distortion on the received

data leads to a dead band in the phase detector transfer function

if phase errors are measured on both rising and falling data

transitions. This dead band leads to jitter generation of

unknown spectral composition whose peak-to-peak amplitude

is potentially large.

The recommended usage of the device when the dc offset loop is

disabled is to compute phase errors exclusively on either the rising

data edges with EDGE_SEL[1:0] (Bits[D4:D3] in Register 0x10) = 1

(decimal) or falling data edges with EDGE_SEL[1:0] = 2. The

alignment of the clock to the rising data edges with EDGE_

SEL[1:0] = 1 is represented by the top two curves in Figure 24.

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