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Data Sheet

ADN2913

Rev. A | Page 23 of 37

Duty cycle distortion with narrow 1s moves the significant

sampling instance where data is sampled to the right of center.

The alignment of the clock to the falling data edges with

EDGE_SEL[1:0] = 2 is represented by the first and third curves

in Figure 24. The significant sampling instance moves to the left

of center. Sample phase adjustment for rates above 5.65 Gbps

can move the significant sampling instance to the center of the

narrow 1 (or narrow 0) for best jitter tolerance.

EDGE_SEL[1:0] = 1

EDGE_SEL[1:0] = 2

CLK1

CLK2

DATA

Figure 24. Phase Detector Timing

DLL Slew

Jitter tolerance beyond the transfer bandwidth of the CDR is

determined by the slew rate of the DLL implementing a delta

modulator on phase. Setting DLL_SLEW[1:0] = 2 (the default

value) in Register 0x13, configures the DLL to track 0.75 UI p-p

jitter at the highest frequency breakpoint in the SONET/SDH

jitter tolerance mask. This frequency scales with the rate as fp4 =

Rate (Hz)/2500 (for example, 1.0 MHz for OC-48). Peak-to-peak

tracking in UI at fp4 obeys the expression (1 + DLL_SLEW)/4 UI

p-p.

In some applications, full SONET/SDH jitter tolerance is not

needed. In this case, DLL_SLEW[1:0] can be set to 0, giving lower

jitter generation on the recovered clock and better high

frequency jitter tolerance.

Sample Phase Adjustment

The phase of the sampling instant can be adjusted using the I2C

interface when the devices operate at data rates of 5.65 Gbps or

higher by writing to SAMPLE_PHASE[3:0] (Bits[D3:D0] in

instant to improve the BER and jitter tolerance. Although the

default sampling instant chosen by the CDR is sufficient in most

applications, when dealing with degraded input signals, the BER

and jitter tolerance performance can be improved by manually

adjusting the phase.

A total adjustment range of 0.5 UI is available, with 0.25 UI in each

direction, in increments of 1/32 UI. SAMPLE_PHASE[3:0] is a

twos complement number. The relationship between data and

the sampling clock is shown in Figure 26.

Transfer Bandwidth

The transfer bandwidth can be adjusted using the I2C interface by

writing to TRANBW[2:0] in Register 0x10. The default value is 4.

When set to values below 4, the transfer bandwidth is reduced.

When set to values above 4, the transfer bandwidth is increased.

The resulting transfer bandwidth is based on the following formula:

















)

(

]

TRANBW[

Transfer

Default

Transfer

For example, at OC-48, the default transfer bandwidth is

650 kHz. The resulting transfer bandwidth when

TRANBW[2:0] is changed is

TRANBW[2:0] = 1: transfer BW = 162.5 kHz

TRANBW[2:0] = 2: transfer BW = 325 kHz

TRANBW[2:0] = 3: transfer BW = 487.5 kHz

TRANBW[2:0] = 4: transfer BW = 650 kHz (default)

TRANBW[2:0] = 5: transfer BW = 812.5 kHz

TRANBW[2:0] = 6: transfer BW = 975 kHz

TRANBW[2:0] = 7: transfer BW = 1137.5 kHz

Reducing the transfer bandwidth is commonly used in OTN

applications. Never set TRANBW[2:0] = 0 because this value

makes the CDR open loop. Also, note that setting TRANBW[2:0]

to a value greater than 4 may cause a slight increase in jitter

generation and potential jitter peaking.

LOSS OF SIGNAL (LOS) DETECTOR

The receiver front-end LOS detector circuit detects when the

input signal level falls below a user adjustable threshold.

There is typically 6 dB of electrical hysteresis on the LOS

detector to prevent chatter on the LOS pin. Therefore, if the

input level falls below the programmed LOS threshold, causing

the LOS pin to assert, the LOS pin is not deasserted until the

input level increases to 6 dB (2×) above the LOS threshold (see

Figure 25).

HYSTERESIS

LOS OUTPUT

INPUT LEVEL

LOS THRESHOLD

Figure 25. LOS Detector Hysteresis

DATA

CLOCK

NOTES

1. PHASE REFERS TO SAMPLE_PHASE[3:0]

PHASE = 4

PHASE = 7

PHASE = –4

PHASE = –8

PHASE = 0

(DEFAULT)

Figure 26. Data vs. Sampling Clock

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