ADN2913 datasheet(25/37 Pages) AD

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Data Sheet

ADN2913

Rev. A | Page 25 of 37

In this case, ensure that the current is a minimum of 6 mA, which

gives a single-ended swing of 300 mV or a differential swing of

600 mV p-p differential, with VCM = 1.05 V (see Figure 33). The

maximum current is 10 mA, which gives a single-ended 500 mV

swing and differential 1.0 V p-p, with VCM = 0.95 V (see Figure 34).

Another possibility is to back terminate the switched current

driver, as shown in Figure 37, with the two VCC supplies having

the same potential. In this example, the current is returned to

VCC by the two 50 Ω resistors in parallel, or 25 Ω, so that the

minimum current is 12 mA and the maximum current is 20 mA.

LOCK DETECTOR OPERATION

The lock detector on the ADN2913 has three modes of opera-

tion: normal mode, LOL detector operation using a reference

clock (LTR mode), and static LOL mode.

Normal Mode

In normal mode, the ADN2913 is a continuous rate CDR that

locks onto any data rate from 6.5 Mbps to 8.5 Gbps without the

use of a reference clock as an acquisition aid. In this mode, the

lock detector monitors the frequency difference between the

DCO and the input data frequency, and deasserts the loss of

lock signal, which appears on LOL, Pin 6, when the DCO is

within 250 ppm of the data frequency. This enables the digital

PLL (D/PLL), which pulls the DCO frequency in the remaining

amount and acquires phase lock. If the input frequency error

exceeds 1000 ppm (0.1%), the loss of lock signal is reasserted

and control returns to the frequency loop, which begins a new

frequency acquisition. The LOL pin remains asserted until the

DCO locks onto a valid input data stream to within 250 ppm

frequency error. This hysteresis is shown in Figure 27.

LOL

–250

250

1000

fDCO ERROR

(ppm)

–1000

Figure 27. Transfer Function of LOL

LOL Detector Operation Using a Reference Clock (LTR

Mode)

In lock to reference (LTR) mode, a reference clock is used as an

acquisition aid to lock the ADN2913 DCO. LTR mode is

enabled by setting CDR_MODE[2:0] to 3 (Bits[D6:D4] in

and DATA_TO_REF_RATIO[3:0] (Bits[D5:D0] in Register 0xF)

to set the reference frequency range and the divide ratio of the

data rate with respect to the reference frequency. Finally, the

reference clock power-down to the reference clock buffer must

be deasserted by writing a 0 to REFCLK_PDN (Bit D2 in

For more information, see the Reference Clock (Optional) section.

In LTR mode, the lock detector monitors the difference in fre-

quency between the divided down DCO and the divided down

reference clock. The loss of lock signal, which appears on LOL

(Pin 6), is deasserted when the DCO is within 250 ppm of the

desired frequency. This enables the D/PLL, which pulls in the

DCO frequency by the remaining amount with respect to the

input data and acquires phase lock. If the frequency error exceeds

1000 ppm (0.1%), the loss of lock signal is reasserted and control

returns to the frequency loop, which reacquires lock with respect to

the reference clock. The LOL pin remains asserted until the DCO

frequency is within 250 ppm of the desired frequency. This

hysteresis is shown in Figure 27.

Static LOL Mode

The ADN2913 implements a static LOL feature that indicates

whether a loss of lock condition has occurred and remains asserted,

even if the ADN2913 regains lock, until the static LOL bit (Bit D2

in Register 0x6) is manually reset. If a loss of lock condition occurs,

this bit is internally asserted to logic high. The static LOL bit

remains high even after the ADN2913 reacquires lock to a new

data rate. This bit can be reset by writing 1, followed by 0, to the

reset static LOL bit (Bit D2 in Register 0x8). When reset, the static

LOL bit remains deasserted until another loss of lock condition

occurs.

Writing a 1 to LOL_CONFIG (Bit D4 in Register 0x9) causes

the LOL pin, Pin 6, to become a static LOL indicator. In this

mode, the LOL pin mirrors the contents of the static LOL bit

(Bit D2 in Register 0x6) and has the functionality described

previously. The LOL_CONFIG bit (Bit D4 in Register 0x9)

defaults to 0. In this mode, the LOL pin operates in the normal

operating mode; that is, it is asserted only when the ADN2913

is in acquisition mode and is deasserted when the ADN2913

has reacquired lock.

HARMONIC DETECTOR

The ADN2913 provides a harmonic detector that detects whether

the input data has changed to a lower harmonic of the data rate

than the one that the sampling clock is currently locked onto. For

example, if the input data instantaneously changes from OC-12,

622.08 Mbps, to an OC-3, 155.52 Mbps bit stream, this change

can be perceived as a valid OC-12 bit stream because the OC-3

data pattern is exactly 4× slower than the OC-12 pattern.

Therefore, if the change in data rate is instantaneous, a 101

pattern at OC-3 is perceived by the ADN2913 as a 111100001111

pattern at OC-12. If the change to a lower harmonic is

instantaneous, a typical inferior CDR may remain locked at the

higher data rate.

The ADN2913 implements a harmonic detector that automati-

cally identifies whether the input data has switched to a lower

harmonic of the data rate than the DCO is currently locked onto.

When a new harmonic is identified, the LOL pin is asserted,

and a new frequency acquisition is initiated. The ADN2913

automatically locks onto the new data rate, and the LOL pin is

deasserted.

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