ADN2913 datasheet(33/37 Pages) AD

33 / 37 page

Data Sheet

ADN2913

Rev. A | Page 33 of 37

APPLICATIONS INFORMATION

TRANSMISSION LINES

Use of 50 Ω transmission lines is required for all high frequency

input and output signals to minimize reflections: PIN, NIN,

CLKOUTP, CLKOUTN, DATOUTP, and DATOUTN (also

REFCLKP and REFCLKN, if using a high frequency reference

clock, such as 155 MHz). The PIN and NIN input traces must be

matched in length, and the CLKOUTP, CLKOUTN, DATOUTP,

and DATOUTN output traces must match in length to avoid

skew between the differential traces.

The high speed inputs (PIN and NIN) are each internally termi-

nated with 50 Ω to an internal reference voltage (see Figure 31).

As with any high speed, mixed-signal circuit, take care to keep

all high speed digital traces away from sensitive analog nodes.

The high speed outputs (DATOUTP, DATOUTN, CLKOUTP, and

CLKOUTN) are internally terminated with 50 Ω to VCC.

SOLDERING GUIDELINES FOR LEAD FRAME CHIP

SCALE PACKAGE

The lands on the 24-lead LFCSP are rectangular. The PCB pad

for the lands is 0.1 mm longer than the package land length, and

0.05 mm wider than the package land width. Center the land on

the pad to ensure that the solder joint size is maximized. The

bottom of the lead frame chip scale package has a central exposed

pad. The pad on the PCB must be at least as large as this exposed

pad. The user must connect the exposed pad to VEE using plugged

vias to prevent solder from leaking through the vias during reflow.

This ensures a solid connection from the exposed pad to VEE.

It is highly recommended to include as many vias as possible

when connecting the exposed pad to VEE. This minimizes the

thermal resistance between the die and VEE, and minimizes the

die temperature. It is recommended that the vias be connected

to a VEE plane, or planes, rather than a signal trace, to improve

heat dissipation, as shown in Figure 38.

Placing an external VEE plane on the backside of the board

opposite the ADN2913 provides an additional benefit because

this allows easier heat dissipation into the ambient environment.

Figure 38. Connecting Vias to VEE

ADN2913 数据表(PDF) 33 Page - Analog Devices

ADN2913 数据表(HTML) 33 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

数据表下载