ADN2913 datasheet(26/37 Pages) AD

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ADN2913

Data Sheet

Rev. A | Page 26 of 37

The time to detect a lock to harmonic is

216 × (Td/ρ)

where:

1/Td is the new data rate. For example, if the data rate is

switched from OC-12 to OC-3, then Td = 1/155.52 MHz.

ρ is the data transition density. Most coding schemes seek to

ensure that ρ = 0.5, for example, PRBS and 8B/10B.

When the ADN2913 is placed in lock to reference mode, the

harmonic detector is disabled.

OUTPUT DISABLE AND SQUELCH

The ADN2913 has two types of output disable/squelch. The

DATOUTP/DATOUTN and CLKOUTP/CLKOUTN outputs

can be disabled by setting DATOUT_DISABLE and CLKOUT_

DISABLE (Bits[D4:D3] in Register 0x1E) high, respectively.

When an output is disabled, it is fully powered down, saving

approximately 30 mW per output. Disabling DATOUTP/

DATOUTN also disables the CLKOUTP/CLKOUTN outputs,

saving a total of about 60 mW of power.

If it is desired to set the data output while leaving the clock

on, the output data can be squelched by setting the data squelch

bit (Bit D5 in Register 0x1E) high. In this mode, the data driver

remains powered, but the data itself is forced to a value of 0 (or

1, depending on the setting of DATA_POLARITY (Bit D1 in

I2C INTERFACE

The ADN2913 supports a 2-wire, I2C-compatible serial bus

driving multiple peripherals. Two inputs, serial data (SDA) and

serial clock (SCK), carry information between any devices con-

nected to the bus. Each slave device is recognized by a unique

address. The slave address consists of the seven MSBs of an 8-bit

word. The upper six bits (Bits[6:1]) of the 7-bit slave address are

factory programmed to 100000. The LSB of the slave address (Bit 0)

is set by Pin 22, I2C_ADDR. The LSB of the word specifies either

a read or write operation (see Figure 18). Logic 1 corresponds to a

read operation, whereas Logic 0 corresponds to a write operation.

To control the device on the bus, the use the following protocol:

The master initiates a data transfer by establishing a start

condition, defined as a high to low transition on SDA while

SCK remains high. This indicates that an address/data

stream follows.

All peripherals respond to the start condition and shift the

next eight bits (the 7-bit address and the R/W bit). The bits

are transferred from MSB to LSB.

The peripheral that recognizes the transmitted address

responds by pulling the data line low during the ninth

clock pulse. This is known as an acknowledge bit.

All other devices withdraw from the bus at this point and

maintain an idle condition. In the idle condition, the

device monitors the SDA and SCK lines waiting for the

start condition and the correct transmitted address.

The R/W bit determines the direction of the data. Logic 0 on the

LSB of the first byte means that the master writes information to

the peripheral. Logic 1 on the LSB of the first byte means that

the master reads information from the peripheral.

The ADN2913 acts as a standard slave device on the bus. The

data on the SDA pin is eight bits long, supporting the 7-bit

addresses plus the R/W bit. The ADN2913 has subaddresses to

enable the user accessible internal registers (see Table 7).

The ADN2913, therefore, interprets the first byte as the device

address and the second byte as the starting subaddress. Auto-

increment mode is supported, allowing data to be read from or

written to the starting subaddress and each subsequent address

without manually addressing the subsequent subaddress. A data

transfer is always terminated by a stop condition. The user can

also access any unique subaddress register on a one-by-one

basis without updating all registers.

Stop and start conditions can be detected at any stage of the

data transfer. If these conditions are asserted out of sequence

with normal read and write operations, they cause an immedi-

ate jump to the idle condition. During a given SCK high period,

issue one start condition, one stop condition, or a single stop

condition followed by a single start condition. If an invalid subad-

dress is issued by the user, the ADN2913 does not issue an

acknowledge and returns to the idle condition. If the user exceeds

the highest subaddress while reading back in auto-increment

mode, the highest subaddress register contents continue to be

output until the master device issues a no acknowledge. This

indicates the end of a read. In a no acknowledge condition, the

SDA line is not pulled low on the ninth pulse. See Figure 20 and

Figure 19 for sample read and write data transfers, respectively,

and Figure 21 for a more detailed timing diagram.

REFERENCE CLOCK (OPTIONAL)

A reference clock is not required to perform clock and data

recovery with the ADN2913. However, support for an optional

reference clock is provided. The reference clock can be driven

differentially or single-ended. If the reference clock is not used,

float both the REFCLKP and REFCLKN pins.

Two 50 Ω series resistors present a differential load between

REFCLKP and REFCLKN. Common mode is internally set to

0.56 × VCC by a resistor divider between VCC and VEE. See

Figure 28, Figure 29, and Figure 30 for sample configurations.

The reference clock input buffer accepts any differential signal

with a peak-to-peak differential amplitude of greater than

100 mV. The phase noise and duty cycle of the reference clock

are not critical, and 100 ppm accuracy is sufficient.

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