ADN2913 datasheet(27/37 Pages) AD

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Data Sheet

ADN2913

Rev. A | Page 27 of 37

50Ω

VCC/2

REFCLKP

REFCLKN

ADN2913

BUFFER

REFCLK

Figure 28. DC-Coupled, Differential REFCLKx Configuration

50Ω

VCC/2

VCC

REFCLKP

OUT

REFCLKN

ADN2913

BUFFER

CLK

OSC

Figure 29. AC-Coupled, Single-Ended REFCLKx Configuration

50Ω

VCC/2

REFCLKP

REFCLKN

ADN2913

BUFFER

REFCLK

Figure 30. AC-Coupled, Differential REFCLKx Configuration

The reference clock can be used either as an acquisition aid for

the ADN2913 to lock onto data, or to measure the frequency

of the incoming data to within 0.01%. The modes are mutually

exclusive because, in the first use, the user can force the device

to lock onto only a known data rate; in the second use, the user

can measure an unknown data rate.

Lock to reference mode is enabled by writing a 3 to CDR_

MODE[2:0] (Bits[D6:D4] in Register 0x8). An on-chip clock

buffer must be powered on by writing a 0 to REFCLK_PDWN

(Bit D2 in Register 0xA). Fine data rate readback mode is enabled

by writing a 1 to RATE_MEAS_EN (Bit D1 in Register 0x8).

Enabling lock to reference and data rate readback at the same

time causes an indeterminate state and is not supported.

Using the Reference Clock to Lock Onto Data

In LTR mode, the ADN2913 locks onto a frequency derived

from the reference clock according to the following equation:

Data Rate/2(LTR_MODE[3:0] − 1) = REFCLK/2LTR_MODE[5:4]

The user must know exactly what the data rate is and provide a

reference clock that is a function of this rate. The ADN2913 can

still be used as a continuous rate device in this configuration if

the user can provide a reference clock that has a variable

frequency (see the AN-632 Application Note).

The reference clock can have a frequency from 11.05 MHz to

176.8 MHz. By default, the ADN2913 expects a reference clock

of between 11.05 MHz and 22.1 MHz. If the reference clock is

between 22.1 MHz and 44.2 MHz, 44.2 MHz and 88.4 MHz, or

between 88.4 MHz and 176.8 MHz, the user must configure the

ADN2913 to use the correct reference frequency range by setting

the two bits of FREF_RANGE[1:0] (Bits[5:4] in Register 0xF).

Table 24. LTR_MODE Register Settings

FREF_RANGE[1:0] Bits Range (MHz)

DATA_TO_REF_

RATIO[3:0] Bits

Ratio

11.05 to 22.1

0000

2−1

22.1 to 44.2

0001

44.2 to 88.4

2n − 1

88.4 to 176.8

1010

The user can specify a fixed integer multiple of the reference clock

to lock onto using DATA_TO_REF_RATIO[3:0] (Bits[D3:D0]

in Register 0xF), as follows:

DATA_TO_REF_RATIO[3:0] = data rate ÷ DIV_fREF

where DIV_fREF represents the divided down reference referred

to the 11.05 MHz to 22.1 MHz band.

For example, if the reference clock frequency is 38.88 MHz and

the input data rate is 622.08 Mbps, then FREF_RANGE[1:0] is

set to 01 to give a divided down reference clock of 19.44 MHz.

DATA_TO_REF_RATIO[3:0] is set to 0110, that is, 6, because

622.08 Mbps/19.44 MHz = 2(6 − 1)

If the ADN2913 is operating in lock to reference mode and the

user changes the reference frequency, that is, the fREF range or the

fREF ratio (Bits[D5:D4] or Bits[D3:D0], respectively, in Register

0xF), this change must be followed by writing a low to high to

low transition to the INIT_FREQ_ACQ bit (Bit D6 in Register 0x9)

to initiate a new lock to reference command.

By default in lock to reference clock mode, when lock has been

achieved and the ADN2913 is in tracking mode, the frequency

of the DCO is compared to the frequency of the reference clock.

If this frequency error exceeds 1000 ppm, lock is lost, LOL is

asserted, and the device relocks to the reference clock while

continuing to output a stable clock.

An alternative configuration is enabled by setting LOL data

(Bit D6 in Register 0xF) = 1. In this configuration, when the device

is in tracking mode, the frequency of the DCO is compared to

the frequency of the input data rather than the frequency of the

reference clock. If the frequency error exceeds 1000 ppm, lock is

lost, LOL is asserted, and the device relocks to the reference

clock while continuing to output a stable clock.

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