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ADN2913 数据表(PDF) 19 Page - Analog Devices

部件名 ADN2913
功能描述  Continuous Rate 6.5 Mbps to 8.5 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ
PDF  37 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADN2913 数据表(HTML) 19 Page - Analog Devices

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Data Sheet
ADN2913
Rev. A | Page 19 of 37
Table 19. Output Swing Register, OUTPUTB (Address 0x1F)
Bits
Bit Name
Bit Description
D7:D4
DATA_SWING[3:0]
Adjust data output amplitude. Step size is approximately 50 mV differential.
Default register value is 0xC. Typical differential data output amplitudes are
0x1 = invalid.
0x2 = invalid.
0x3 = invalid.
0x4 = 200 mV.
0x5 = 250 mV.
0x6 = 300 mV.
0x7 = 345 mV.
0x8 = 390 mV.
0x9 = 440 mV.
0xA = 485 mV.
0xB = 530 mV.
0xC = 575 mV.
0xD = 610 mV.
0xE = 640 mV.
0xF = 655 mV.
D3:D0
CLOCK_SWING[3:0]
Adjust clock output amplitude. Step size is approximately 50 mV differential.
Default register value is 0xC. Typical differential clock output amplitudes are
0x1 = invalid.
0x2 = invalid.
0x3 = invalid.
0x4 = 200 mV.
0x5 = 250 mV.
0x6 = 300 mV.
0x7 = 345 mV.
0x8 = 390 mV.
0x9 = 440 mV.
0xA = 485 mV.
0xB = 530 mV.
0xC = 575 mV.
0xD = 610 mV.
0xE = 640 mV.
0xF = 655 mV.



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