ADN2913 datasheet(29/37 Pages) AD

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Data Sheet

ADN2913

Rev. A | Page 29 of 37

Four oscillator cores defined by VCOSEL[9:8] (Bits[D1:D0] in

Table 25.

Table 25. DCO Center Frequency vs. VCOSEL[9:8]

Core =

VCOSEL[9:8]

Min Frequency

(MHz) = Min_f(core)

Max Frequency

(MHz) = Max_f(core)

5570

7105

7000

8685

8610

10,330

10,265

11,625

fDCO is determined from VCOSEL[9:0] (Bits[D7:D0] in

following formula:

fDCO =

]

VCOSEL[

core

Min

core

Max

core

Min

256

)

(

)

(

)

(







Worked Example

Read back the contents of the FREQ_RB1 and FREQ_RB2

registers. For example, with an OC-48 signal presented to the

PIN/NIN ports,

FREQ_RB1 = 0xCD

FREQ_RB2 = 0x46

FULLRATE (FREQ_RB2[6]) = 1

DIVRATE[3:0] (FREQ_RB2[5:2]) = 1

VCOSEL[9:8] core (FREQ_RB2[1:0]) = 2

Then

fDCO =

Mbps

9987

205

256

Mbps

8610

Mbps

300

Mbps

8610









and

Mbps

2496

Mbps

9987







data

Initiate Frequency Acquisition

A frequency acquisition can be initiated by writing a 1 followed

by a 0 to INIT_FREQ_ACQ (Bit D6 in Register 0x9). This initiates

a new frequency acquisition while keeping the ADN2913 in the

operating mode that was previously programmed in Register 0x8,

registers, respectively).

PRBS Generator/Receiver

The ADN2913 has an integrated PRBS generator and detector

for system testing purposes. The device is configurable as either

a PRBS detector or a PRBS generator.

The following steps configure the PRBS detector:

Set DATA_RECEIVER_ENABLE (Bit D2 in Register 0x3F)

to 1 and set DATA_RECEIVER_MODE[1:0] (Bits[D1:D0]

in Register 0x3F) according to the desired PRBS pattern

(0 = PRBS7; 1 = PRBS15; 2 = PRBS31). Setting DATA_

RECEIVER_MODE[1:0] to 3 leads to a one-shot sampling

of recovered data into DATA_LOADED[15:0].

Set DATA_RECEIVER_CLEAR (Bit D3 in Register 0x3F)

to 1 followed by 0 to clear PRBS_ERROR and

PRBS_ERROR_COUNT[7:0].

States of PRBS_ERROR (Bit D1 in Register 0x41) and

PRBS_ERROR_COUNT[7:0] (Bits[D7:D0] in Register 0x40)

can be frozen by setting DATA_RECEIVER_ENABLE (Bit D2

in Register 0x3F) to 0.

The following steps configure the PRBS generator:

Set DATA_GEN_EN (Bit D2 in Register 0x39) = 1 to

enable the PRBS generator and set DATA_GEN_MODE[1:0]

(Bits[D1:D0] in Register 0x39) for the desired PRBS output

pattern (0 = PRBS7; 1 = PRBS15; 2 = PRBS31). An arbitrary

32-bit pattern stored as PROG_DATA[31:0] is activated by

setting DATA_GEN_MODE[1:0] to 3.

Strings of consecutive identical digits (CIDs) of sensed

DATA_CID_ BIT (Bit D5 in Register 0x39) can be

introduced in the generator by setting DATA_CID_EN

(Bit D4 in Register 0x39) set to 1. The length of CIDs is 8 ×

DATA_CID_LENGTH, which is set via Bits[D7:D0] in

Table 26. PRBS Settings

PRBS Pattern

DATA_GEN_MODE[1:0]

PRBS Polynomial

PRBS7

1 + X6 + X7

PRBS15

1 + X14 + X15

PRBS31

1 + X28 + X31

PROG_DATA[31:0]

N/A

Double Data Rate Mode

The default output clock mode is a double data rate (DDR)

clock, where the output clock frequency is one-half the data

rate. DDR mode allows direct interfacing to FPGAs that support

clocking on both rising and falling edges. Setting DDR_DISABLE

(Bit D2 in Register 0x1E) = 1 enables full data rate mode. Full

data rate mode is not supported for data rates in the highest

octave between 5.6 Gbps and 8.5 Gbps.

CDR Bypass Mode

The CDR in the ADN2913 can be bypassed by setting the

CDR bypass bit (Bit D5 in Register 0x9) = 1. In this mode, the

ADN2913 feeds the input directly through the input amplifiers

to the output buffer, bypassing the CDR. The CDR bypass path is

intended for use in testing or debugging a system. Use the CDR

bypass path at data rates at or below 3.0 Gbps only.

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