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LP8725TLE-A/NOPB 数据表(PDF) 14 Page - Texas Instruments

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部件名 LP8725TLE-A/NOPB
功能描述  LP8725 Power Management Unit for Application or Multimedia Processors and Subsystems
PDF  46 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

LP8725TLE-A/NOPB 数据表(HTML) 14 Page - Texas Instruments

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EN
Buck 1
0 1 2 3
Buck 2
tBON
tS
START UP sequence
Timing Code
SHUT DOWN sequence
is in reverse order of START UP sequence
Timing Code
Buck 1
0
1
2
3
Buck 2
LDO1
LDO1
LDO3
LDO3
START UP
tS
tS
tS
tS
tS
tS
tS
tS
tS
tS
tS
SHUT DOWN
IDLE
Note 4
LDO4
LDO4
LDO5
LDO5
LILO 2
LILO 2
LILO 1
LILO 1
4 5 6
6 5 4
LDO2
LDO2
EN
Note 3
Note 3
Note 5
Note 3
Note 3
STANDBY
STANDBY
LP8725
SNVS618G – DECEMBER 2009 – REVISED MAY 2013
www.ti.com
Figure 10. LP8725-B Startup and Shutdown Sequence if CONFIG=GND,
DEFSEL=VIN1 or DEFSEL=GND Note 1, Note 2
All timing is typical.
tBON 75 µs - Reference and bias turn ON.
tS Programmable time steps. (Typically 64 µs/step.) Time step accuracy is defined by OSC frequency accuracy.
Note 1 STARTUP and SHUT DOWN sequences are defined by registers. Sequences given here are valid if there the
registers are not rewritten via Serial Interface.
Note 2 The timing showed here define time points when LDOs and BUCK are enabled/disabled. Enabling /disabling
process duration depends on voltages and loading conditions. Buck startup duration is typically 170 µs. LDO startup
duration is typically 35 µs. For details please see LDOs and BUCK Electrical Specifications.
Note 3 LDO2, 4, 5 and LILO1 are disabled. If they are enabled via Serial Interface and the startup sequence is not
changed, then they will be disabled, with no delay, from falling edge of EN-pin.
Note 4 At this time point registers are reset to POR default values.
Note 5 LDO3 is enabled by LDO3_EN (or via serial interface). If this input is high when PWR_ON goes high then this
output turns on after ts= 6.
14
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Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LP8725



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