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LP8725TLE-A/NOPB 数据表(PDF) 26 Page - Texas Instruments

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部件名 LP8725TLE-A/NOPB
功能描述  LP8725 Power Management Unit for Application or Multimedia Processors and Subsystems
PDF  46 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

LP8725TLE-A/NOPB 数据表(HTML) 26 Page - Texas Instruments

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LP8725
SNVS618G – DECEMBER 2009 – REVISED MAY 2013
www.ti.com
Table 9. Control Register Defaults (continued)
LP8725 Defaults: DEFSEL state
LP8725-A Defaults: DEFSEL state
LP8725-B Defaults: DEFSEL state
ADDR
VIN1
GND
VIN1
GND
VIN1
GND
0x0D
0111 1111
0111 1111
1111 1011
1111 1111
0100 0001
0100 0001
0x0E
0111 1111
0111 1111
0111 1111
0111 1111
0111 1111
0111 1111
0x0F
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
LP8725-C Defaults: DEFSEL state
LP8725-D Defaults: DEFSEL state
ADDR
VIN1
GND
VIN1
GND
0x00
1101 1101
1101 1101
1001 1101
1001 1101
0x01
1001 0101
1001 0101
1111 1001
1111 1001
0x02
1001 1001
1001 1001
1110 1100
1110 1100
0x03
1011 1001
1011 1001
0100 1100
0100 1100
0x04
1011 0100
1011 0100
1111 1101
1111 1101
0x05
0101 1111
0101 1111
1110 0000
1110 1100
0x06
1000 1000
1000 1000
0101 1101
0101 1101
0x07
1000 1000
1000 1000
0101 1101
0101 1101
0x08
0000 1000
0000 1000
0000 1010
0000 1010
0x09
1100 1000
1100 1000
1100 1010
1100 1010
0x0A
0101 0001
0101 0001
0101 0001
0101 0001
0x0B
1001 0001
1001 0001
1101 0001
1101 0001
0x0C
0001 0001
0001 0001
0001 0001
0001 0001
0x0D
0111 1111
0111 1111
0110 0100
0110 0100
0x0E
0111 1111
0111 1111
0111 1111
0111 1111
0x0F
0000 0000
0000 0000
0000 0000
0000 0000
Table 10. Register 0X00
Addr
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit2
Bit 1
Bit 0
0x00
GENERAL
TIMESTEP
SHORT_
BUCK2_E
DVS2_V
DVS1_V
SLEEP_MO
BUCK1_EN
TIMESTEP
N
DE
BUCK1_EN
BUCK1, BUCK2 enable control
BUCK2_EN
In STANDBY mode
In IDLE mode the bit has immediate effect.
1: During next STARTUP sequence will be enabled.
1: Enable
0: During next STARTUP sequence will be NOT
0: Disable
enabled
For proper operation output timing having “111 - NO
startup” should have corresponding enable bit 0
(disable)
SLEEP_MODE
LDO Sleep Control
1: SLEEP mode
0: normal
DVS1_V
1: drive buck voltage to value stored in BUCK1_V1[4:0]
0: Buck output voltage controlled by external DVS pin.
DVS2_V
1: drive buck voltage to value stored in BUCK2_V1[4:0]
0: Buck output voltage to value stored in BUCK2_V2[4:0]
SHORT_TIMESTEP
TIMESTEP = 0
TIMESTEP = 1
TIMESTEP
SHORT_TIMESTEP = 0 — time step ts = 32 µs
SHORT_TIMESTEP = 0 — time step ts = 128 µs
SHORT_TIMESTEP = 1 — time step ts = 64 µs
SHORT_TIMESTEP = 1— time step ts = 256 µs
26
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