LP8725

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SNVS618G – DECEMBER 2009 – REVISED MAY 2013

Analog-Type LDOs

The analog LDOs are optimized for supplying analog loads having ULTRA LOW NOISE (10 µVRMS for

interface for different output voltage values.

For fast discharging of output capacitors in shutdown, the LDOs may be connected to a 300

Ω pull down resistor

to output.

In sleep mode quiescent current is lowered down to 30 µA for energy saving. In this mode these LDOs should

not loaded more than 3-5 mA of output current.

Digital-Type LDOs

The Digital LDOs are optimized for dynamic performance for fast changing digital loads whilst consuming very

little quiescent current ~ 20 µA . They can be programmed through serial interface for different output voltage

values.

For fast discharging of output capacitors in shutdown, the LDOs may be connected to a 300

Ω pull down resistor

to output.

In sleep mode quiescent current is lowered down to 10 µA for energy saving. In this mode these LDOs should

not loaded more than 3-5 mA of output current.

LILO-Type LDOs

The LILO-type LDO is optimized for low output voltage and for good dynamic performance to supply different fast

changing (digital) loads. These LDOs can be operated as digital LDOs also albeit with lower PSRR and Noise

performance.

An innovative design of the all the LDOs reduces sensitivity to the placement of the output capacitor. The output

capacitor may not be placed as close as possible to the output pin, like on conventional LDOs. The general

purpose LDOs do not need output capacitor close to the PMU. If a (1 µF or more) capacitor is attached to a

circuit load, customer may skip the output capacitor at the PMU.

I

Interface Bus Overview

the device.

This protocol uses a two-wire interface for bi-directional communications between the ICs connected to the bus.

The two interface lines are the Serial Data Line (SDA), and the Serial Clock Line (SCL). These lines should be

connected to a positive supply, via a pull-up resistor of 1.5 K

Ω and remain HIGH even when the bus is idle.

Every device on the bus is assigned a unique address and acts as either a Master or a Slave depending on

whether it generates or receives the serial clock (SCL).

Data Transactions

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the

SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction. New

data should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

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