LP8725

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SNVS618G – DECEMBER 2009 – REVISED MAY 2013

PIN DESCRIPTIONS

Name

Pin No.

Description

CONFIG=0: B2_EN is the enable for BUCK2 output if this pin is high and if BUCK2_EN register bit is set to

B2_EN/PS_HOLD

B3

0. (B2_EN and the register bit are logical OR.) Internal 500 K

Ω pull-down resistor in this configuration only.

CONFIG=1: PS_HOLD is a power supply hold input from an external processor.

CONFIG

E2

Connect to GND for SUB_PMU or connect to VIN1 for PMU.

Control input that sets default voltages and start-up sequence. Must be hard wired to VIN1 or GND for

specific application.

DEFSEL

D2

When DEFSEL=VIN1 then setup 1 is used for default voltages and startup sequences.

When DEFSEL=GND then setup 2 is used for default voltages and startup sequences.

Dynamic Voltage Scaling (operational when REG 0x00<2> is '0').

DVS=1 then BUCK voltage set BUCK1_V1 is in use.

DVS

C2

DVS=0 then BUCK voltage set BUCK1_V2 is in use.

This pin must be driven to its logic high or low whenever the BUCK1 or BUCK2 outputs are enabled.

CONFIG=0: EN=1 turns on outputs or standby mode if EN=0.

EN/PWR_ON

E3

CONFIG=1: PWR_ON=1 starts power up sequence after 30 ms of de-bounce time. Internal 500K pull-

down resistor.

FB1

E4

BUCK1 Feedback. Active pull-down when BUCK1 turns off.

FB2

B4

BUCK2 Feedback. Active pull-down when BUCK2 turns off.

GND

D3

IC Ground

GNDB1

F5

BUCK1 Ground.

GNDB2

A5

BUCK2 Ground.

LDO1

F1

LDO1 output.

LDO2

E1

LDO2 output.

LDO3

C1

LDO3 output.

LDO3_EN

B2

Enable for LDO3 output if this pin is high and if LDO3_EN register bit is set to 0. (LDO3_EN and the

register bit are logical OR.) Internal 500 K

Ω pull-down resistor.

LDO4

A1

LDO4 output.

LDO5

B1

LDO5 output

LILO1

F3

LILO1 output.

LILO2

A3

LILO2 output.

CONFIG=0: Goes high typ. 30 ms after EN=1 and goes low when EN=0.

RESET_N

C3

CONFIG=1: Goes high typ. 60 ms after PWR_ON=1 and goes low 30 ms after PS_HOLD=0.

External pull-up resistor is needed, typical 10 k

Ω.

SCL

D4

Serial Interface Clock Input. External pull-up resistor is needed, typical 1.5 k

Ω.

SDA

C4

Serial Interface Data Input/Output. Open Drain output, external pull-up resistor is needed, typical 1.5 k

Ω.

SW1

E5

BUCK1 Switch node of DC-DC converter BUCK1.

SW2

B5

BUCK2 Switch node of DC-DC converter BUCK2.

VIN1

F2

Input for LDO1.

VINB1

D5

Input for BUCK1.

VIN2

D1

Input for LDO2 and LDO3.

VINB2

C5

Input for BUCK2.

VIN3

A2

Input for LDO4 and LDO5.

VINLILO1

F4

Input for LILO1.

VINLILO2

A4

Input for LILO2.

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

Copyright © 2009–2013, Texas Instruments Incorporated

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